Offending Segment | Multi-Tech Systems RAS96 specification

B POST Messages

OFFENDING SEGMENT:

This message is used in conjunction with the I/O CHANNEL CHECK and RAM PARITY ERROR messages when the segment that has caused the problem has been isolated.

PRESS A KEY TO REBOOT

This will be displayed at the bottom screen when an error occurs that requires you to reboot. Press any key and the system will reboot.

PRESS F1 TO DISABLE NMI, F2 TO REBOOT

If BIOS detects a non-maskable interrupt (NMI) during boot, this will allow you to disable the NMI and continue to boot, or you can reboot the system with the NMI enabled.

RAM PARITY ERROR - CHECKING FOR SEGMENT ...

Indicates a parity error in random access memory.

CommPlete Communications Server

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Multi-Tech Systems RAS96 manual Offending Segment

Contents

RAS96 RASCard E1 User Guide RAS96 RASCard User Guide Iii Important Safety Instructions Table of Contents Appendix C Post Codes Solving ProblemsPage Introduction Manual Organization Introduction Appendix B Post Messages Technical SpecificationsAppendix C Post Codes Appendix D Approved Memory Humidity range 20-90% noncondensing RASCard Description RAS96 RASCard Memory Banks J14, J15, J16, J18 CPU Frequency Selection J17 Watchdog TimerJumpers Internal Connectors J2 Power Connector External ConnectorsJ22 E1 Alarm J35 Video Front Panel LED IndicatorsEthernet Status LEDs E1 Status LEDs Reset Switch SwitchesPower Switch Page Installation Installation Procedure Safety WarningsPre-Installation Notes Installation Page Bios Setup Utility Starting Setup Getting Help Using SetupCase of Problems Bios Features Setup Standard Cmos SetupChipset Features Setup Power Management Setup Load Bios Defaults PCI Configuration SetupPassword Setting IDE HDD Auto Detection Load Setup Defaults Exit Without Saving Save and Exit Setup Date Standard Cmos SetupTime Hard Disks CGA Drive a Type / Drive B TypeVideo Memory Halt On Enabled Bios Features SetupDisabled Virus Warning Boot Sequence Quick Power On Self TestBoot Up Floppy Seek Boot Up NumLock Status Gate A20 Option Typematic Rate SettingMemory Parity Check Typematic Rate Chars/Sec Video Bios Shadow Typematic Delay MsecSecurity Option C8000 Cffff Shadow/DC000 Dffff Shadow Dram Timing Chipset Features SetupSystem Bios Cacheable Bit I/O Recovery Time Video Bios CacheableIDE HDD Block Mode Memory Hole At 15M-16M PCI Concurrancy On-Chip Primary PCI IDEPCI Streaming PCI Bursting Power Management Power Management Setup Standby Mode Doze ModeSuspend Mode HDD Power Down COM Ports Accessed Power Down ActivitiesLPT Ports Accessed Drive Ports Accessed 1st/2nd/3rd/4th Available IRQ PCI Configuration SetupSlot x Using INT# PCI IDE IRQ Map to PCI IRQ Activated by Enter Password Password SettingPage E1 Daughter Cards E1 Overview Specifications E1 Glossary E1 Basics E1 Frame Formats Signaling OptionsE1 Line Coding Dnis digits Country Selection E1 Facility Termination Pin Signal PCB Description RJ-11 Alarm JackE1 Line Monitoring Jack Test Modes Ordering an E1 Line Configuration of the E1 Daughter CardChannelized E1 line with 30 DS-0 channels E1 Frame Format Line Coding Factory Defaults To Configure the E1 Daughter Card Command Example E1 Commands RAS96 RASCard User Guide E1 Daughter Card RAS96 RASCard User Guide E1 Status LEDs E1 Command Messages Functional Description Solving Problems RASCard has no video Troubleshooting Keyboard does not respond to key strokes Invalid time, date or setupCOM1 port does not respond correctly Memory Upgrade Calling Technical Support Diagnostic Tests RAS96 RASCard User Guide Appendixes Video Connector J35 Appendix a Connector PinoutsKeyboard Connector J11 E1 Alarm Connector J22 COM1 Connector J3 Drive Power Connector J13 Pin Floppy Disk Drive Connector J27 IOCS16 Hard Disk Connector J6 Figure A-7. IDE connector IDE Connector J21 Post Beep Error MessagesAppendix B Post Messages Memory Verify Error at Memory Address Error atMemory parity Error at Offending Segment Code Name Description Appendix C Post Codes Post Codes E1-EF Capacity Speed Type Manufacturer Part Number Usable MB Appendix D Approved Memory Appendix E Regulatory Information EMC, Safety and Terminal Directive Compliance