Index
©
National Instruments Corporation I-7 AT-MIO-16X User Manual
example switch settings (figure), 2-3
switch settings, with base I/O address
and address space (table),
2-5 to 2-6
DMA channel selection, 2-7
interrupt channel selection, 2-7
Configuration and Status Register Group,
4-4 to 4-30
Command Register 1, 4-5 to 4-8
Command Register 2
description, 4-9 to 4-12
interrupt programming, 5-43
programming digital I/O
circuitry, 5-36
Command Register 3, 4-13 to 4-19
Command Register 4, 4-20 to 4-24
overview, 4-4
register map, 4-1
Status Register 1
description, 4-25 to 4-29
servicing update requests, 5-36
Status Register 2, 4-30
connectors. See I/O connectors.
continuous channel scanning
definition, 5-10
programming, 5-10 to 5-11
continuous scanning data acquisition
timing, 3-13
counter block diagram, 3-27
counter signal connections, 2-37 to 2-42
concatenating counters, 2-39
event-counting application, 2-37 to 2-38
frequency measurements, 2-39
input and output ratings, 2-40
overview, 2-37
pulse-width measurements, 2-38
time-lapse measurements, 2-38
timing requirements (figure), 2-41
timing specifications, 2-40 to 2-43
counter/timer. See Am9513A Counter/Timer
Register Group; Am9513A System Timing
Controller.
customer communication, xvii, D-1 to D-2
cyclic waveform generation. See DAC
waveform circuitry and timing; waveform
generation programming.
CYCLICSTOP bit
cyclic waveform generation, 3-22, 5-26
description, 4-23
D
D<15..0> bit
Am9513A Data Register, 4-65
DAC0 Register, 4-44
DAC1 Register, 4-45
D<15..0> bits
ADC FIFO Register, 4-32 to 4-33
DAC Clear Register
clearing analog output circuitry, 5-32
description, 4-56
DMA operations, 5-41
servicing update requests, 5-36
DAC Event Strobe Register Group,
4-53 to 4-56
DAC Clear Register
clearing analog output circuitry, 5-32
description, 4-56
DMA operations, 5-41
servicing update requests, 5-36
DAC Update Register, 4-55
register map, 4-2
TMRREQ Clear Register
clearing analog output circuitry, 5-32
description, 4-54
DMA operations, 5-41
interrupt programming, 5-43
servicing update requests,
5-35 to 5-36