Chapter 2. Installation and Setup | |
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| HAS S | CO N |
| DIS |
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| T IM P | 15 0 | LO W | J 13 |
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| C | J 14 |
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| X M |
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| R CV IM P | 1 50 | H IG H | J 10 |
| M T LVL | 0 d bm |
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| J 12 |
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| X |
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| RC V LVL | LO W | HIG H |
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| R PF. | O N | O FF |
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| J 9 |
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| J 11 * |
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| R LB D TE |
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| AL B DTE |
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| EN | D IS | EN |
| DIS |
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| J 7 |
| J 8 |
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| 3 | 4 5 | 6 | E |
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| 2 |
| B AU D R AT kbps |
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| 4 - 115 .2 5 - 112 |
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| 9 - 57 .6 |
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| C - 38 .4 |
| E - 2 8 .8 | F - 19 .2 | |||
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| 1 |
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| 7 | 0 - 256 | 1 - 192 | 2 - 144 | 3 - 128 | 6 - 96 | 7 - 72 | 8 - 64 | A - 5 6 | B - 4 8 | D - 32 | ||||||||
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| 0 |
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| F E D C B A | |||||||||||||||||||||
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| S W 3 |
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| % |
| 12 | 2 5 |
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| BIT P TO S |
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| O N |
| 3 | B IT | 8 9 | 1 0 | 11 |
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| S W 2 |
| ON |
| 2 | LN 1 | O F F | O F F O N O N |
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| O N |
| 1 | L N0 | O F F | O N |
| O N |
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| CAR RIER |
| C NTRL |
| XM T CL K |
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| J 6 |
V 54 D IS | EN | DIS | O N |
| IN T E X T R C V A S Y |
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| 0 9 70 | RTS |
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| SW . E N . | O N | O FF | |||||||
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| J 2 |
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| J 3 |
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| J 4 |
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*J11 - Only for standalone option
Warning
Note
Figure 2-3 PCB Layout Diagram
In certain locations where permanent excessive high voltages are present on the lines, disconnecting the signal ground from the chassis ground may render the unit unsafe for connection to unprotected telecommunication networks.
For applications using an X.21 interface external clock (DTE timing source), connect the input clock to Pins 7(a) and 14(b) of the
In X.21, one of the modems should be set to RCV clock.
Table