Bank Select, Ffff, Mao | Sharp MZ-3500 instruction

MZ3500

Operational description

(1)As soon as the sub-CPU is started, it initializes the I/O port and waits for program transfer (IOCS) from the main CPU. This IOCS (Input Output Control System) is the program resident at address 4000H-5FFFH.

(2)As the main CPU loads the information from sector

Communication between Main and SUB CPU

2:3. SD2 (ROM based BASIC)

SD2 is active when "SHARP BASIC" is executed via ROM.

"1" of track "0" of the floppy disk, it loads the IOCS and bootstrap routine to the sub-CPU.

(3)The bootstrap program is loaded next.

(4)The bootstrap program determines rnemory allocation.

BUSRQ H OUTPUT

(ISOLATION OFCOM RAM)

															M S] = I (H)
								M A I N		C P U					MSO = 0 Li	SUB CPU
	M A S 0 0			0 0 0 0					0	0	1	1	1	I	1
BANK	M A 2 °	0	°	0	0 .		0	1	1	1	0	0	0	0	1
SELECT	M A I	0	0	1		1	0	0	I	I	0	0	1	I	0
	MAO	0	1		0	1	0	1	0	1	0	1	0	1	0

FFFF	1			I I I
	1			I I I
i	R\MA				KAMB
i
Sffi	4	1	1,	2,	3	4
Sffi
i\	2
	3

IFF?

ROME ROMC ROMU ROM! ROM 2

IFF?

JROMA

000 0

(MO2		0	0	0	0		1
(MO2
M	O	1 0	0		1		1	0
M	O	O	0		1	0	1	0

1	1		1	1	1	1
	K \M L				K A M I !
1 1	2	3,	4	1 1	2, 3	4

1.Bank select,MAO~MA3. is effective for memory area COOOH-FFF FH.

2.Bank select, MOO~MA2, is effective for memory area 2000H-3FFFH

- 10 -

Image 11

Sharp MZ-3500 service manual Bank Select, Ffff, Mao

Contents

Personal Computer Model Z-350 Video TimerBACKUP, INIT, COPY, DEBUG, Killall Memory SFDI/F Refer to the page TIN Circuit DiagramSlot Slot2 LSI, 1C Cmosic Change Disp PresetSymbol Sdisp User Basic Area RAMBase System MZ-1D07 MZ3500 System configuration of Model MS1 = D MSO = 0 L Software Memory Configuration Timing of Reset Signal ROM-IPL SD1 System Loading & CP/M MAO Bank SelectFfff ROM SD3 RAM based BasicOperational description Bank Main Memory Mapper Block diagram Relation between MMR main memory Table below describes address map Main CPU and I/O portThis paragraph discusses main CPU I/O Sub CPU and I/O port 0001Main CPU \m MZ3500 Coab Memory mapper MMRSP6102R-001 Block diagramTo Reset Address BUS Srdy MZ3500 Memory mapper MMR SP6102R-001 signal descriptionRAS ROW Address Select Line Address Select Signal Pin No RO2B IN/OUTRO1B 1 1 1 1 1 1 FF 14 I N D3 A7 A6 A5A4A3A2AlAO H E X Uhus 1 O1 1 1 1 0 KI1 Dl Do 17 D6 D5 D2 Dl 1 1 1 1 1 0 FE do D4 D3 MZ3500 Memory ROMIPL, RAMCOM, S-RAM select circuit CRT Specification Asci Summary of video display specification Graphic dot Dot pitchBlue Dot color designated by CH AI +,! AT A r + + G CH ATKA7 Ascii CG #1 FFF Video RAM Structure of Vram #0000 Structure of character Vram When read/write from GDC#07FFA 8bit Read/write by Z-80 via the GDC 640 x 200 dots display mode FV = 60 Hz 16K O signal switching 640 x 400 bits display mode FH = 20.92 kHz FV = 47.3 HzSetup of GCD master/slave Master/slave setup by combination Graphic V-RAM Address Crtc block diagramPage Master slice LSI CSP-1 SP6102C 002 signal description CSH CSP-1 Block Diagram» CK HSY2 2BLK2 LSI CSP-2 SP6012C-003 Signal Description CAS OUT CSP 2 Block Diagram3r00 DSP2 OUT GDC Graphic display controller UPD7220 signal description CSR-1MAGE AD15ILC2NK-CLC AT~BTI Structure CG Address Select Circuit Circuit description Vsync Blsc Character Vram select circuit Read/write from the Z-80 to V-RAM Set GDC command code Fifo Empty? Return when all parameters were sentCsrw C 49H -COMMAND Code Write C 23H Command Code Vecte C 6CH Command Code Following manner Dot display program example-1 60HExplanation VECTE. Dot address is structured on the screen Kind of line solid line I T E C 23HP4 88H P5 HH Outline Floppy disk TJ ILJ n Ci D ci Ici VnVn n nV nnn7 Data MZ3500 MFD interface block diagram 22 «- o Window FDC UPD765 UPD765 signal description MFM recording method Trigger motor on of the timer 555 Selects FDDMZ350C Port used in the MFD interface is as follows Control during seek and recalibration Controls during read, write, seek, and re- calibrateMedia detection 3500 Precompensate Circuit Purpose String of data Pulses from the FDD Data window VFO circuit Filter Phase Detector Amplifier Window VFO circuit configuration BQA MFM Mode FM mode timing chart \\\\ 3DSC Side =Aload Indicates the byte position From the top of directory 76 iy 7 EH 77 / FFH\128 Track 10 sector 1015 Ii PatatB144 6145 B146 B147 39 B148 B149 B150 B151 39 B74 B75 Example 7-bits, even parity, 1 stop bit General specificationData transmission format MZS500 OFF AC controlsStart 8251 AC MZ3500 Data output controlKTS RXEN,UTR , T X E N 3SOO 128 2009 6.3 256 «--N Wl -» 8253 OUT 8253 DS7 Printer interfacing circuitAA3 DAT Data transfer timing General description of the parallel interfaceOutput I/O port map DIN Clock circuit SchematicRead Hold Write Hold SET LSB MSB MZ3500 PD1990AC Block diagram » GETE1 J Mmmil SFD 1/F 3500S I C GP I/O FD2 SW2 SW1 On on CE332P OFF on MZ1P02 On OFF IO2824 OFF OFFDipswa SEC \f Canbe in either state Description of each block Block diagramFunctions +5V Switching regulator Timing chart Alarm generation circuit Key Specification of keyboard controlAt rrn Strobe Key search timing2s 2s22 21 Key Protocol Key to sub CPU 132.522.5/-s Keyboard controller basic flow ALE DBO DB7 GND Keyboard controller signal descriptionXTAL1 XTAL2 Reset INT PIN On OFF Sub-CPU side Procedure S C I I 00-FF Shared RAMCRT inter face test Abnormal Ready O.H Abnormal test ending1 5 c * O DR O.7 ROM-IPL Main CPU Checker Flow Chart 1/2 100 Main CPU Checker Flow Chart M? M7*500 101 Keyboard test Keyboard controller ROM test IPL Flow Chart Load Iocs SEEK& Read Jump \ Boot Address SystemSEEK, Read Error Error 105 SUB CPU IPL Flow Chart R R R R F1 LJ LJ LJ LJ LJ LJ LJ U J l J J L i J L L j l J J L l J L L l LU LU U LJ LlJ LJ U U RoB IwCAIO MZ-35OO Parts Guide LI S C R I P T I O N No Parts CodeLED PWB IE--or Ooss-zw Qcnw MZ-3500Parts Code N T K S C R I P T I O N Connector A a N a D MZ-3500NO. Parts Code Parts Code NEW VH S N 7 4 0 6 N Coos Part S C R I P T I O NMark Rank M2-3500 J9, MZ1K02,1K03,1K04,1K05 Key unit NO. Parts Code SOCLSI RAM LA a D e Tin N a a Parts Code MZ-3500 Sharp Corporation