MZ3500 PD1990AC Block diagram, Lsb Msb | Sharp MZ-3500 manual

MZ3500

3)^PD1990AC Block diagram

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Command specification
C2	C1	CO	Command
0	0	0	Register hold
0	0	1	Register shift
0	1	0	Time set
0	1	1	Time read

Description

Holds 40-bit S/R

Data input/output

Data of the 40-bit S/R is preset to the time counter.

Data in the time counter is read to the 40-bit S/R.

		DOUT	Data Shift	Note
	1Hz		Not possible	Data retention
	[LSB]	Output of LSB	Possible	Shifts in synchronization
	[LSB]	Output of LSB	Possible	with the clock
				with the clock
	ILSB]	Output	Not possible
	[LSB]	Output	Not possible

Input/output format

Example: In the case of 10 o'clock, 25 minutes, 49 seconds, July 30th.

(LSB)								(MSB)
9	4	5	2	0	1	0	3	7
«- Seconds—' L(\/jnutes—I				Lnoure_)		L_Dey—I		Wo!OnthJ

- 82 -

Image 75

Sharp MZ-3500 service manual MZ3500 PD1990AC Block diagram, Lsb Msb

Contents

Personal Computer Model Z-350 Video TimerBACKUP, INIT, COPY, DEBUG, Killall Memory SFDI/F Refer to the page TIN Circuit DiagramSlot Slot2 LSI, 1C Cmosic Change Disp PresetSymbol Sdisp User Basic Area RAMBase System MZ-1D07 MZ3500 System configuration of Model MS1 = D MSO = 0 L Software Memory Configuration Timing of Reset Signal ROM-IPL SD1 System Loading & CP/M Bank Select FfffMAO ROM SD3 RAM based BasicOperational description Bank Main Memory Mapper Block diagram Relation between MMR main memory Main CPU and I/O port This paragraph discusses main CPU I/OTable below describes address map Sub CPU and I/O port 0001Main CPU \m MZ3500 Coab Memory mapper MMRSP6102R-001 Block diagramTo Reset Address BUS MZ3500 Memory mapper MMR SP6102R-001 signal description RAS ROW Address Select Line Address Select SignalSrdy Pin No IN/OUT RO1BRO2B 1 1 1 1 1 1 FF 14 I N D3 A7 A6 A5A4A3A2AlAO H E X Uhus 1 O1 1 1 1 0 KI1 Dl Do 17 D6 D5 D2 Dl 1 1 1 1 1 0 FE do D4 D3 MZ3500 Memory ROMIPL, RAMCOM, S-RAM select circuit CRT Specification Asci Summary of video display specification Graphic dot Dot pitchBlue Dot color designated by CH AT KA7CH AI +,! AT A r + + G Ascii CG #1 FFF Video RAM Structure of Vram Structure of character Vram When read/write from GDC #07FFA#0000 8bit Read/write by Z-80 via the GDC 640 x 200 dots display mode FV = 60 Hz 16K O signal switching 640 x 400 bits display mode FH = 20.92 kHz FV = 47.3 HzSetup of GCD master/slave Master/slave setup by combination Graphic V-RAM Address Crtc block diagramPage Master slice LSI CSP-1 SP6102C 002 signal description CSP-1 Block Diagram » CKCSH HSY2 2BLK2 LSI CSP-2 SP6012C-003 Signal Description CAS OUT CSP 2 Block Diagram3r00 DSP2 OUT GDC Graphic display controller UPD7220 signal description CSR-1MAGE AD15ILC2NK-CLC AT~BTI Structure CG Address Select Circuit Circuit description Vsync Blsc Character Vram select circuit Read/write from the Z-80 to V-RAM Set GDC command code Fifo Empty? Return when all parameters were sentCsrw C 49H -COMMAND Code Write C 23H Command Code Vecte C 6CH Command Code Following manner Dot display program example-1 60HExplanation VECTE. Dot address is structured on the screen I T E C 23H P4 88H P5 HHKind of line solid line Outline Floppy disk TJ ILJ n Ci D ci Ici VnVn n nV nnn7 Data MZ3500 MFD interface block diagram 22 «- o Window FDC UPD765 UPD765 signal description MFM recording method Trigger motor on of the timer 555 Selects FDDMZ350C Port used in the MFD interface is as follows Control during seek and recalibration Controls during read, write, seek, and re- calibrateMedia detection 3500 Precompensate Circuit Purpose String of data Pulses from the FDD Data window VFO circuit Filter Phase Detector Amplifier Window VFO circuit configuration BQA MFM Mode FM mode timing chart \\\\ Side = Aload3DSC Indicates the byte position From the top of directory 76 iy 7 EH 77 / FFH\128 Track 10 sector 1015 Ii PatatB144 6145 B146 B147 39 B148 B149 B150 B151 39 B74 B75 Example 7-bits, even parity, 1 stop bit General specificationData transmission format MZS500 AC controls StartOFF MZ3500 Data output control KTS8251 AC RXEN,UTR , T X E N 3SOO 128 2009 6.3 256 «--N Wl -» 8253 OUT 8253 DS7 Printer interfacing circuitAA3 DAT General description of the parallel interface OutputData transfer timing I/O port map DIN Clock circuit SchematicRead Hold Write Hold SET LSB MSB MZ3500 PD1990AC Block diagram » GETE1 J Mmmil SFD 1/F 3500S I C GP I/O FD2 SW2 SW1 On on CE332P OFF on MZ1P02 On OFF IO2824 OFF OFFDipswa SEC \f Canbe in either state Block diagram FunctionsDescription of each block +5V Switching regulator Timing chart Alarm generation circuit Specification of keyboard control At rrnKey Strobe Key search timing2s 2s22 21 Key 132.5 22.5/-sProtocol Key to sub CPU Keyboard controller basic flow ALE DBO DB7 GND Keyboard controller signal descriptionXTAL1 XTAL2 Reset INT PIN On OFF Sub-CPU side Procedure S C I I 00-FF Shared RAMCRT inter face test Abnormal Abnormal test ending 1 5 c * O DR O.7Ready O.H ROM-IPL Main CPU Checker Flow Chart 1/2 100 Main CPU Checker Flow Chart M? M7*500 101 Keyboard test Keyboard controller ROM test IPL Flow Chart Load Iocs SEEK& Read Jump \ Boot Address SystemSEEK, Read Error Error 105 SUB CPU IPL Flow Chart R R R R F1 LJ LJ LJ LJ LJ LJ LJ U J l J J L i J L L j l J J L l J L L l LU LU U LJ LlJ LJ U U IwC AIORoB MZ-35OO Parts Guide LI No Parts Code LED PWBS C R I P T I O N IE--or Ooss-zw Qcnw MZ-3500Parts Code N T K S C R I P T I O N Connector A a N a D MZ-3500NO. Parts Code Parts Code NEW VH S N 7 4 0 6 N Part S C R I P T I O N Mark RankCoos M2-3500 J9, MZ1K02,1K03,1K04,1K05 Key unit NO. Parts Code SOCLSI RAM LA a D e Tin N a a Parts Code MZ-3500 Sharp Corporation