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MZ3500
46.LSI (CSP-2) SP6012C-003 Signal Description
Polarity
IN/OUT
Signal Name
1 HSY2 IN
2BLK2 IN
Horizontal synchronizing signal from GDC2 which also becomes the refresh tirniny . i j r . s ' i in the dynamic RAM mode.
Erase signal input from the GDC2 which is supplied 4T the following times:
1.Horizotal flyback period.
2.Vertical flyback period.
3.Period from the execution of the SYNC SET command to
4.Line drawing period.
3OWE OUT
4 - 5
6DBI2 IN
7DBI1IN
8BUSG OUT
9SOE OUT
10SWE OUT
110816OUT
12 RAS1IN
13 RAS2 IN
14ASSIN
15 NWRO IN
18 RA40 IN
19M40IN
20GNDIN
21SL2 OUT
22 RASA OUT
23 2CM2 OUT
24 LOAD OUT
25VccIN
26 FYD2 OUT
27 2CK1OUT
28SL1 OUT
29SL1 OUT
30 CGOE OUT
RAS-B
WRITE ENABLE output for the graphic dynamic RAM.
Input of the display output signals (AD14, AD1 5) from GDC2. (Used to create
Input from the GDC2 by which the image memory output is sent on the data bus. (Used to create
Input from the GDC1 by which the image memory output is sent on the data bus. (Used to create BUSG, SOE, SWE in the
Gate signal of the bidirection bus buffer (LS245) which is used to read/write attribute, and character, data from the static RAM (21
OUTPUT ENABLE for character static RAM (61
WRITE ENABLE for attribute, character static RAM.
Memory control signal RAS from GDC1. (Used to create CGOE, SL1 in
Memory control signal RAS from CDC3.
(Used to create SL2, LOAD,
Address bus input from the
Chip select (OUT#5X) of the I/O port in
Data bus input from the
The signal that goes to high level (input from
Clock input from the clock generator (39.32MHz, for
0V supply
Graphic DRAM output parallel/serial converter 1C 74LS166 shift load signal.
Graphic DRAM (A), (B) RAS signal.
Double character clock output. In the character display mode, a single phase clock of the half the one character wide frequency is supplied. In the graphic display mode, a single phase clock of 8/16 dot frequency is supplied to GDC2.
Graphic DRAM output parallel/serial converter 1C 74LS166 load timing clock.
+5V supply.
Graphic DRAM output parallel/serial converter 1C 74LS166 shift out clock.
Double character clock output same as 2CK2. In the character display mode, a single phase clock of one half the one character wide frequency is supplied to GDC1 .
Character CG output parallel/serial converter 1C 74LS166 shift out clock.
Character CG output parallel/serial converter 1C LS166 shift load signal.
Character CG address.
Character CG output enable signal.
Timing signal by which the graphic DRAM output is sent on the data bus.
Graphic DRAM RAS (ROW ADDRESS SELECT) signal
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