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Sharp MZ-3500 service manual 16K, FV = 60 Hz

Models: MZ-3500

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			M Z 3500
(2) 640 x 400 dots display mode		B/W:	1 frame
		B/W:	1 frame
		Color:	1 frame
Option I
( 4 8 K b y t e )	# 4 0 0 0		Color can be
16 bits structure	# 3 KKK	# 3 F F F	i designated for
			sach character.
		16K	16K
	* 0 0 0 0	# 0 0 0 0

( B F FF	B/W:	3 frames
Option II
(96K byte)	Color:	1 frame
16 bits structure
# 8 0 0 0

#3FFF

# 4 0 0 0

#0000

16K

# 0 0 0 0

16bit

5)Synchronize signal timing

(1)For 640 x 200 dots display mode

	fH = 15.87kHz
	fV =	60 Hz
			GDC-1 (80 digits)
			Character display (40 digits)
	Dot clock (OD)		(16MHz)
	Dot clock (OD)		( 8MHz)
			( 8MHz)
	2XCCLK		(4MHz)
	2XCCLK		<2MHz>
			<2MHz>
	Horizontal	display time	40MS
	HFP		?A«
			?A«
	HS		6>js
	HBP		10/js
	Vertical display time		1 2.6ms
	VFP		1.2ms
			1.2ms
	VS		1 ms
	VBP		1.8ms

16K

16bit 16bit 16bit

	X : Y - 1 : 2
GDC-2	graphic)
8 bits	16 bits
16MHz	16MHz
4MHz	2MHz
-	-
•^(14 Chr.)	10MS
(1?Chr )	5^s
(tREF-0.8ms)	( t R E F = 1.6ms)
- (20 Chr.)	8ns
-	-
-	j
	j
-	-
-	-

Total rasters: 261 rasters

Display raster: 200 rasters	•—-n.
	1 r~-

Image 30

Sharp MZ-3500 service manual 16K, FV = 60 Hz

Contents

Personal Computer Model Z-350 Memory TimerBACKUP, INIT, COPY, DEBUG, Killall VideoLSI, 1C Cmosic Refer to the page TIN Circuit DiagramSlot Slot2 SFDI/FSdisp PresetSymbol Change DispSystem Basic Area RAMBase UserMZ-1D07 MZ3500 System configuration of Model Software Memory Configuration MS1 = D MSO = 0 LTiming of Reset Signal SD1 System Loading & CP/M ROM-IPLBank Select FfffMAO Bank SD3 RAM based BasicOperational description ROMBlock diagram Relation between MMR main memory Main Memory MapperMain CPU and I/O port This paragraph discusses main CPU I/OTable below describes address map MZ3500 0001Main CPU \m Sub CPU and I/O portAddress BUS Memory mapper MMRSP6102R-001 Block diagramTo Reset CoabMZ3500 Memory mapper MMR SP6102R-001 signal description RAS ROW Address Select Line Address Select SignalSrdy Pin No IN/OUT RO1BRO2B D2 Dl 1 1 1 1 1 0 FE do D4 D3 A7 A6 A5A4A3A2AlAO H E X Uhus 1 O1 1 1 1 0 KI1 Dl Do 17 D6 D5 1 1 1 1 1 1 FF 14 I N D3MZ3500 Memory ROMIPL, RAMCOM, S-RAM select circuit Specification CRTSummary of video display specification AsciDot color designated by Dot pitchBlue Graphic dotCH AT KA7CH AI +,! AT A r + + G #1 FFF Ascii CGVideo RAM Structure of Vram Structure of character Vram When read/write from GDC #07FFA#0000 Read/write by Z-80 via the GDC 640 x 200 dots display mode 8bit16K FV = 60 HzMaster/slave setup by combination 640 x 400 bits display mode FH = 20.92 kHz FV = 47.3 HzSetup of GCD master/slave O signal switchingCrtc block diagram Graphic V-RAM AddressPage Master slice LSI CSP-1 SP6102C 002 signal description CSP-1 Block Diagram » CKCSH LSI CSP-2 SP6012C-003 Signal Description HSY2 2BLK2DSP2 OUT CSP 2 Block Diagram3r00 CAS OUTGDC Graphic display controller UPD7220 signal description AT~BTI AD15ILC2NK-CLC CSR-1MAGECG Address Select Circuit StructureVsync Circuit descriptionCharacter Vram select circuit BlscSet GDC command code Read/write from the Z-80 to V-RAMWrite C 23H Command Code Vecte C 6CH Command Code Return when all parameters were sentCsrw C 49H -COMMAND Code Fifo Empty?VECTE. Dot address is structured on the screen 60HExplanation Following manner Dot display program example-1I T E C 23H P4 88H P5 HHKind of line solid line Floppy disk OutlineTJ ILJ n VnVn n nV nnn7 Ci D ci IciData MZ3500 MFD interface block diagram FDC UPD765 22 «- o WindowUPD765 signal description Port used in the MFD interface is as follows Trigger motor on of the timer 555 Selects FDDMZ350C MFM recording method3500 Precompensate Circuit Controls during read, write, seek, and re- calibrateMedia detection Control during seek and recalibrationVFO circuit Purpose String of data Pulses from the FDD Data windowVFO circuit configuration Filter Phase Detector Amplifier WindowMFM Mode BQAFM mode timing chart \\\\ Side = Aload3DSC Track 10 sector 76 iy 7 EH 77 / FFH\128 Indicates the byte position From the top of directory39 B74 B75 Ii PatatB144 6145 B146 B147 39 B148 B149 B150 B151 1015MZS500 General specificationData transmission format Example 7-bits, even parity, 1 stop bitAC controls StartOFF MZ3500 Data output control KTS8251 AC 3SOO RXEN,UTR , T X E N256 2009 6.3 128Wl -» «--N8253 8253 OUTDAT Printer interfacing circuitAA3 DS7General description of the parallel interface OutputData transfer timing I/O port map Write Hold SET Clock circuit SchematicRead Hold DINMZ3500 PD1990AC Block diagram LSB MSBMmmil » GETE1 JGP I/O 3500S I C SFD 1/FSEC SW2 SW1 On on CE332P OFF on MZ1P02 On OFF IO2824 OFF OFFDipswa FD2\f Canbe in either state Block diagram FunctionsDescription of each block Switching regulator +5VAlarm generation circuit Timing chartSpecification of keyboard control At rrnKey Key Key search timing2s 2s22 21 Strobe132.5 22.5/-sProtocol Key to sub CPU Keyboard controller basic flow PIN Keyboard controller signal descriptionXTAL1 XTAL2 Reset INT ALE DBO DB7 GNDOn OFF Procedure Sub-CPU sideAbnormal Shared RAMCRT inter face test S C I I 00-FFAbnormal test ending 1 5 c * O DR O.7Ready O.H ROM-IPL Main CPU Checker Flow Chart 1/2 Main CPU Checker Flow Chart M? 100101 M7*500Keyboard controller ROM test Keyboard testIPL Flow Chart Error Jump \ Boot Address SystemSEEK, Read Error Load Iocs SEEK& ReadSUB CPU IPL Flow Chart 105LJ LJ LJ LJ LJ LJ LJ R R R R F1LU LU U LJ LlJ LJ U U U J l J J L i J L L j l J J L l J L L lIwC AIORoB MZ-35OO Parts Guide LI No Parts Code LED PWBS C R I P T I O N IE--or Ooss-zw N T K MZ-3500Parts Code QcnwConnector S C R I P T I O NParts Code MZ-3500NO. Parts Code A a N a DVH S N 7 4 0 6 N NEWPart S C R I P T I O N Mark RankCoos J9, MZ1K02,1K03,1K04,1K05 Key unit M2-3500LA a SOCLSI RAM NO. Parts CodeD e Tin Parts Code N a aMZ-3500 Sharp Corporation