Sharp MZ-3500 service manual 200, 9 6.3, 256, 128

6-6. 8253 Controls

Baud rate of this interface will be determined by the clock output of the 8253. The 8251 is configured such that its baud rate is 1/16 of the input clock and has the following relation between the 8253 output clock and the baud rate:

8253 input frequency: 2457.6kHz

8253 Mode set: Mode 3(rec'angle waveform rategenerator)

			MZ 3500
Baud rale		8253	8253
		Output frequency	Parameter
	1 1 0 .t -	1 7 6 0 H z	1 3 9 6.3 6
	300	4 8 0 0	51 2
	600	9 6 00	256
1	200	1 9 2 0 0	128
2 4 0 0		3 8 4 0 0	64
4 8 0 0		7 6 8 0 0	32
9 6 0 0		153600	1 6

Control signals

Signal name	Symbol	IN/OUT	Function
Transmission enabled	CS	-* Peripheral	When high, data input from a peripheral is enabled.
			When low, data input from a peripheral is disabled.
Data set ready	DR	— Peripheral	Goes high when power is on to the interface unit.
Carrier detect	CD	— Peripheral	(SW6-ON) High at all times when power is on to the interface unit.
			(SW6-OFF) Goes high only when data is on output.
Ready	READY	— Peripheral	Data output from the interface isenabled.
			(ON) Data is output from the interface.
			(OFF) Waits for data output.
			NOTE: A maximum of two bytes are output after the signal goes from high to low
			state.
Equipment ready	ER	«- Peripheral	Indicates that the peripheral is ready. It results in an error if low or open when data
			is sent from the interface. This signal will be invalidated when the SW5 is turned
			off.
Paper out	PO	<- Peripheral	(SW7-ON) Causes an error if set high during data output.
			(SW7-OFF) Causes an error if set low during data output.

6-7. Description of LSI's

1)UPD8251AC (Programmable Communication Interface) The UPD8251A is a USART (Universal Synchronous/ Asynchronous Receiver/Transmitter that was specifical- ly designed for data communication.

The USART receives parallel data from the CPU and converts it into serial data before transmitting. Also, serial data is received from an external circuit and trans- ferred to the CPU after converting it into parallel. The CPU can monitor the current state of the USART at any time (data transfer error, and control signal of

,SYNDETandTXEMPTY.

,-eatures

•8080A/8085A compatible

•Synchronous/asychronous operation

•Synchronous operation 5 —8 bits character

Clock rate: baud rate x 1, x16, x64 BREAK character generation Stop bit: 1, 1.5, 2 bits

Error start bit detection

Automatic break detection and operation.

•Baud rate: DC - 64Kbaud

•Full-duplex

Double buffer type transmitter/receiver

•Error detect

Parity, overrun, framing

•Input/output TTL compatible

•N-channel MOS

•Single +5Vsupply

•Single phase TTL level clock

•28-pin, plastic DIP

•Intel 8251A compatible

Pin configuration (Top View)

<28 »OD1

3?5 PORTS' 422-0 DSR

-i-2—XDTXEMPTY

3*12-0 CT3

SYNDET BD TXRDY

Block diagram

		Data			1
			8	„«.	Transmission
1)7-1)004 8 »		bus
		buffer
				8	t *
			8
RESET O	»•	Read/			Transmissic>n	_
					control '	X>TXE
		write
					34	OTXC
		control
		logic			Reception
				8
					buffer
		*			( S -• P )
Dsko	m				t 1
			^_
		MOOhM
					Receiver
t rscx— x: controller			8
				^	control
k'l so*	c					H I )

V

Internal data bus^

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