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6-6. 8253 Controls
Baud rate of this interface will be determined by the clock output of the 8253. The 8251 is configured such that its baud rate is 1/16 of the input clock and has the following relation between the 8253 output clock and the baud rate:
8253 input frequency: 2457.6kHz
8253 Mode set: Mode 3(rec'angle waveform rategenerator)
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Baud rale | 8253 | 8253 | ||
Output frequency | Parameter | |||
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| 1 1 0 .t - | 1 7 6 0 H z | 1 3 9 6.3 6 | |
| 300 | 4 8 0 0 | 51 2 | |
| 600 | 9 6 00 | 256 | |
1 | 200 | 1 9 2 0 0 | 128 | |
2 4 0 0 | 3 8 4 0 0 | 64 | ||
4 8 0 0 | 7 6 8 0 0 | 32 | ||
9 6 0 0 | 153600 | 1 6 |
Control signals
Signal name | Symbol | IN/OUT | Function |
Transmission enabled | CS | When high, data input from a peripheral is enabled. | |
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| When low, data input from a peripheral is disabled. |
Data set ready | DR | — Peripheral | Goes high when power is on to the interface unit. |
Carrier detect | CD | — Peripheral | |
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Ready | READY | — Peripheral | Data output from the interface isenabled. |
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| (ON) Data is output from the interface. |
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| (OFF) Waits for data output. |
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| NOTE: A maximum of two bytes are output after the signal goes from high to low |
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Equipment ready | ER | «- Peripheral | Indicates that the peripheral is ready. It results in an error if low or open when data |
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| is sent from the interface. This signal will be invalidated when the SW5 is turned |
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| off. |
Paper out | PO | <- Peripheral | |
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6-7. Description of LSI's
1)UPD8251AC (Programmable Communication Interface) The UPD8251A is a USART (Universal Synchronous/ Asynchronous Receiver/Transmitter that was specifical- ly designed for data communication.
The USART receives parallel data from the CPU and converts it into serial data before transmitting. Also, serial data is received from an external circuit and trans- ferred to the CPU after converting it into parallel. The CPU can monitor the current state of the USART at any time (data transfer error, and control signal of
,SYNDETandTXEMPTY.
•8080A/8085A compatible
•Synchronous/asychronous operation
•Synchronous operation 5
Clock rate: baud rate x 1, x16, x64 BREAK character generation Stop bit: 1, 1.5, 2 bits
Error start bit detection
Automatic break detection and operation.
•Baud rate: DC - 64Kbaud
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Double buffer type transmitter/receiver
•Error detect
Parity, overrun, framing
•Input/output TTL compatible
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•Single +5Vsupply
•Single phase TTL level clock
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•Intel 8251A compatible
Pin configuration (Top View)
<28 »OD1
3?5 PORTS'
SYNDET BD TXRDY
Block diagram
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| 8 | „«. | Transmission |
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bus |
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| buffer |
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| 8 | t * |
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RESET O | »• | Read/ |
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| control ' | X>TXE | |||
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| write |
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| 34 | OTXC | |
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| buffer |
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Dsko | m |
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| MOOhM |
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t rscx— x: controller | 8 |
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^ | control |
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k'l so* | c |
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V
Internal data bus^
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