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Sharp MZ-3500 service manual Alarm generation circuit, Timing chart

Models: MZ-3500

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M23500

c. Power switching circuit

As the signal from the oscillator is amplified through Q7 to Q6 to change current to the transformer T2. it causes voltage to appear on the base of Q5 (one of components is cut by D1), so that the transistor Q5 begins to per- form switching operation in synchronization with the oscillation frequency. As Q2 is switched, current is supplied to the emitter side of the transistor Q5, which produces smoothed voltage through the capacitor C1 and the coil L2. The circuit composed of D4 and VR1 is the reference voltage for the +5 or + 12V supply, which is used to control the emitter current flowing to the transistor Q9. The current supplied from Q9 is used to create Tr3 inactive by the delayed C1 and C2 voltages which supplied from Tr1-R2-VR1-D3. It goes high with deactivation of Tr3.

3. Alarm circuit

(Alarm generation circuit)

When power turns off, the voltage accumulated in C1 and C2 are supplied to the base of Tr2 via Tr1 ... and D3, so that Tr2 is kept active and Tr3 inactive for some- times after power off.

Timing chart

SW

+ 5V

PFD

-89 -

Image 82

Sharp MZ-3500 service manual Alarm generation circuit, Timing chart

Contents

Personal Computer Model Z-350 Memory TimerBACKUP, INIT, COPY, DEBUG, Killall VideoLSI, 1C Cmosic Refer to the page TIN Circuit DiagramSlot Slot2 SFDI/FSdisp PresetSymbol Change DispSystem Basic Area RAMBase UserMZ-1D07 MZ3500 System configuration of Model Software Memory Configuration MS1 = D MSO = 0 LTiming of Reset Signal SD1 System Loading & CP/M ROM-IPLFfff Bank SelectMAO Bank SD3 RAM based BasicOperational description ROMBlock diagram Relation between MMR main memory Main Memory MapperThis paragraph discusses main CPU I/O Main CPU and I/O portTable below describes address map MZ3500 0001Main CPU \m Sub CPU and I/O portAddress BUS Memory mapper MMRSP6102R-001 Block diagramTo Reset CoabRAS ROW Address Select Line Address Select Signal MZ3500 Memory mapper MMR SP6102R-001 signal descriptionSrdy Pin No RO1B IN/OUTRO2B D2 Dl 1 1 1 1 1 0 FE do D4 D3 A7 A6 A5A4A3A2AlAO H E X Uhus 1 O1 1 1 1 0 KI1 Dl Do 17 D6 D5 1 1 1 1 1 1 FF 14 I N D3MZ3500 Memory ROMIPL, RAMCOM, S-RAM select circuit Specification CRTSummary of video display specification AsciDot color designated by Dot pitchBlue Graphic dotKA7 CH ATCH AI +,! AT A r + + G #1 FFF Ascii CGVideo RAM Structure of Vram #07FFA Structure of character Vram When read/write from GDC#0000 Read/write by Z-80 via the GDC 640 x 200 dots display mode 8bit16K FV = 60 HzMaster/slave setup by combination 640 x 400 bits display mode FH = 20.92 kHz FV = 47.3 HzSetup of GCD master/slave O signal switchingCrtc block diagram Graphic V-RAM AddressPage Master slice LSI CSP-1 SP6102C 002 signal description » CK CSP-1 Block DiagramCSH LSI CSP-2 SP6012C-003 Signal Description HSY2 2BLK2DSP2 OUT CSP 2 Block Diagram3r00 CAS OUTGDC Graphic display controller UPD7220 signal description AT~BTI AD15ILC2NK-CLC CSR-1MAGECG Address Select Circuit StructureVsync Circuit descriptionCharacter Vram select circuit BlscSet GDC command code Read/write from the Z-80 to V-RAMWrite C 23H Command Code Vecte C 6CH Command Code Return when all parameters were sentCsrw C 49H -COMMAND Code Fifo Empty?VECTE. Dot address is structured on the screen 60HExplanation Following manner Dot display program example-1P4 88H P5 HH I T E C 23HKind of line solid line Floppy disk OutlineTJ ILJ n VnVn n nV nnn7 Ci D ci IciData MZ3500 MFD interface block diagram FDC UPD765 22 «- o WindowUPD765 signal description Port used in the MFD interface is as follows Trigger motor on of the timer 555 Selects FDDMZ350C MFM recording method3500 Precompensate Circuit Controls during read, write, seek, and re- calibrateMedia detection Control during seek and recalibrationVFO circuit Purpose String of data Pulses from the FDD Data windowVFO circuit configuration Filter Phase Detector Amplifier WindowMFM Mode BQAFM mode timing chart \\\\ Aload Side =3DSC Track 10 sector 76 iy 7 EH 77 / FFH\128 Indicates the byte position From the top of directory39 B74 B75 Ii PatatB144 6145 B146 B147 39 B148 B149 B150 B151 1015MZS500 General specificationData transmission format Example 7-bits, even parity, 1 stop bitStart AC controlsOFF KTS MZ3500 Data output control8251 AC 3SOO RXEN,UTR , T X E N256 2009 6.3 128Wl -» «--N8253 8253 OUTDAT Printer interfacing circuitAA3 DS7Output General description of the parallel interfaceData transfer timing I/O port map Write Hold SET Clock circuit SchematicRead Hold DINMZ3500 PD1990AC Block diagram LSB MSBMmmil » GETE1 JGP I/O 3500S I C SFD 1/FSEC SW2 SW1 On on CE332P OFF on MZ1P02 On OFF IO2824 OFF OFFDipswa FD2\f Canbe in either state Functions Block diagramDescription of each block Switching regulator +5VAlarm generation circuit Timing chartAt rrn Specification of keyboard controlKey Key Key search timing2s 2s22 21 Strobe22.5/-s 132.5Protocol Key to sub CPU Keyboard controller basic flow PIN Keyboard controller signal descriptionXTAL1 XTAL2 Reset INT ALE DBO DB7 GNDOn OFF Procedure Sub-CPU sideAbnormal Shared RAMCRT inter face test S C I I 00-FF1 5 c * O DR O.7 Abnormal test endingReady O.H ROM-IPL Main CPU Checker Flow Chart 1/2 Main CPU Checker Flow Chart M? 100101 M7*500Keyboard controller ROM test Keyboard testIPL Flow Chart Error Jump \ Boot Address SystemSEEK, Read Error Load Iocs SEEK& ReadSUB CPU IPL Flow Chart 105LJ LJ LJ LJ LJ LJ LJ R R R R F1LU LU U LJ LlJ LJ U U U J l J J L i J L L j l J J L l J L L lAIO IwCRoB MZ-35OO Parts Guide LI LED PWB No Parts CodeS C R I P T I O N IE--or Ooss-zw N T K MZ-3500Parts Code QcnwConnector S C R I P T I O NParts Code MZ-3500NO. Parts Code A a N a DVH S N 7 4 0 6 N NEWMark Rank Part S C R I P T I O NCoos J9, MZ1K02,1K03,1K04,1K05 Key unit M2-3500LA a SOCLSI RAM NO. Parts CodeD e Tin Parts Code N a aMZ-3500 Sharp Corporation