Polarity
Pin No.
Signal Name
32RF1B
33RF2B
34WATB
35RCMB
36ITFB
37ITOB
38IT1B
39TT2B
40MRQB
41WRB
42IT3B
43IT4B
44SEC
45GND
46Vcc
47SW1
48SW2
49AO
50RFSH
51SW3
52SW4
53GND
54FD1
55Vcc
56FD2
M 7, 3500
IN/OUT |
| Function |
|
OUT | Main CPU 128KB dynamic RAM output buffer (LS244) output enable signal. | ||
| (RAM | buffer 1) | |
|
| ||
OUT | Signal identical to R F1 B | For option RAM |
|
| (RAM | buffer 2) | |
|
| ||
| Wait signal to the mam CPU |
|
|
OUT | (One wait cycle 15 applied during the memory fetch cycle of the main CPU. It consists of one clock | ||
| period) | (WAT) |
|
| Chip select signal issued from the mam CPU to select the RAM shared by the main CPU and | ||
OUT | the |
|
|
|
| (RAM Common) | |
Interrupt input from the UPD765 FDC (Floppy Disk Controller).
IN
(Interrupt from Floppy)
Interrupt input from the
IN
(Interrupt from No. 0)
Interrupt input from slot 1 or 2.
IN
(Interrupt from No. 1, 2)
Memory request signal from the main CPU.
IN
(Memory Request)
Write signal from the main CPU.
IN
(Write)
Interrupt input from slot 3 or 4.
IN
(Interrupt from No. 3, 4)
Input from the FDD (Floppy Disk Drive) assignment dip switch (A), No. 1.
IN 'See the dip switch description, provided separately. (Section)
IN Ground
IN | 5V supply |
Input from Thesvstem assignment dip switch,
IN
"See the dip switch description, provided separately.
Mam CPU address bus
IN
Used rn the I/O port select logic in the MMR to designate device number.
Refresh signal from the main CPU.
IN
(Refresh)
Input from the system assignment dip switch.
IN
•See the dip switch description, provided separately.
IN Ground
Input from the system assignment dip switch.
IN
'See the dip switch description, provided separately.
IN | 5V supply. |
Input from the FDD assignment dip switch (A), No. 2.
IN
*See the dip swi'ch description, provided separately.
