Sharp MZ-3500 service manual Main CPU and I/O port, This paragraph discusses main CPU I/O

MZ3500

3-2. Main CPU and I/O port

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							This paragraph discusses main CPU I/O
					Connector		Port select and addressing.
						I PC 2	The address output from the main CPU
	A2				~^T		1 is decoded in the 74LS138 to create the
	A3	j^		""	v		select signal.
				~s	f^-r-^r-.—r		Table below describes address map and
			Y 1
	A4			~~>	\J>	-•> r DL	signal functions.
			iZ	J	\J I Obr
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A6	A v~\ r	(jtA.	Y3
M	P C
	IORQ		Y4	-)	f\
		G2 B		J	-\J
			Y5	^	0 MFUC
	M i	Ol	Y6		• \J	lUMr

5 O IOABCMEMORY MAPPER)

74LSI38

ADDRESS

A7 A6 A5 A4 A3 A2 A1 AO									HEX
0	0	0	0	0	0	0	0		00
0	0	0	0	0	0	0	1		01
										NOT USE
1	1	0	1	1	1	1	0		DE
1	1	0	1	1	1	1	1		DF
									EO
^	^		^	Q		o	o	x	x	NOT USE
									E3
									E4
^	^		^	Q		O	•	^	x	x SFDC (UPD765)
									E 7
									E8
i	i	i	o		t	o	x	x		IOSF
									EB
									EC
1 1 1 0 1					1	X .	X			INTR
									EF
									FO
1	1	1	1		Q	O	X	X		NOT USE
									F3
									F4

SFD interface FDC chip select.

AO used for RD and WR.

A1 is "don't care".

SFD interface I/O port and DMAC chip select.

Interrupt signal from the sub-CPU to the main CPU. Flipflop resetting signal.

1 1 1 1 0 1 X X MFDC (UPD765) MFD interface FDC chip select.

F 7

								F8
1	1	1	1	1	0	X	X	IOMF
								F B
								FC
1	1	1	1	1	1	X	X	IOAB (MEMORY MAPPER)
								F F

MFD interface I/O port.

AO used for RD and WR.

AT is "don't care".

I/O port select in the memory mapper. AO and A1 used during ~W5. WR.