General specification, Data transmission format | Sharp MZ-3500

MZS500

6. R232C INTERFACE

6-1. General specification

Input/output format

No of channels

Code used

Baud rate

Transmission system

Synchronization method

Communication control procedure

Data format

LSI used

RS-232C bit serial input/output

1 channel

JIS 7-channel/JIS 8 channel

110 to 9600 bits/sec

Half-duplex

Start-stop

Non-procedure

Stop bif 1/1.5/2, with or without even or odd parity.

8251 AC or8253C-5 (Programmable interval Timer)

6-2. Data transmission format

	2°	21	22	23	24	25	26
7-bit,
with parity
v	„ _ i \							j v__^___/
Start bit			Data bit		(7 bits)			Parity bit Stop bit (1 or 2 bits)
7-bit,
without parity
V	XV				X	V	X	'

Start bit

Data bit (7 bits)

8-bit

with parity

V• w •' V	^ ^ _
Start bit	Data bit (8 bits)

8-bit, without parity

v

Try

Start bit

Data bit (8 bits)

Example: 7-bits, even parity, 1 stop bit

Start bit

7-bit data (26H)

Stop bit of precedingdata

Stop bit

Parity bit Stop bit (1 or 2 bits)

,

Y

Stop bit (1 or 2 bit

Parity bit	Start bit of
	succeeding data

Stop bit

- 7) -

Image 64

Sharp MZ-3500 General specification, Data transmission format, MZS500, Example 7-bits, even parity, 1 stop bit

Contents

Personal Computer Model Z-350 Timer BACKUP, INIT, COPY, DEBUG, KillallMemory Video Refer to the page TIN Circuit Diagram Slot Slot2LSI, 1C Cmosic SFDI/F Preset SymbolSdisp Change Disp Basic Area RAM BaseSystem User MZ-1D07 MZ3500 System configuration of Model Software Memory Configuration MS1 = D MSO = 0 L Timing of Reset Signal SD1 System Loading & CP/M ROM-IPL Ffff Bank SelectMAO SD3 RAM based Basic Operational descriptionBank ROM Block diagram Relation between MMR main memory Main Memory Mapper This paragraph discusses main CPU I/O Main CPU and I/O portTable below describes address map 0001 Main CPU \mMZ3500 Sub CPU and I/O port Memory mapper MMRSP6102R-001 Block diagram To ResetAddress BUS Coab RAS ROW Address Select Line Address Select Signal MZ3500 Memory mapper MMR SP6102R-001 signal descriptionSrdy Pin No RO1B IN/OUTRO2B A7 A6 A5A4A3A2AlAO H E X Uhus 1 O 1 1 1 1 0 KI1 Dl Do 17 D6 D5D2 Dl 1 1 1 1 1 0 FE do D4 D3 1 1 1 1 1 1 FF 14 I N D3 MZ3500 Memory ROMIPL, RAMCOM, S-RAM select circuit Specification CRT Summary of video display specification Asci Dot pitch BlueDot color designated by Graphic dot KA7 CH ATCH AI +,! AT A r + + G #1 FFF Ascii CG Video RAM Structure of Vram #07FFA Structure of character Vram When read/write from GDC#0000 Read/write by Z-80 via the GDC 640 x 200 dots display mode 8bit 16K FV = 60 Hz 640 x 400 bits display mode FH = 20.92 kHz FV = 47.3 Hz Setup of GCD master/slaveMaster/slave setup by combination O signal switching Crtc block diagram Graphic V-RAM AddressPage Master slice LSI CSP-1 SP6102C 002 signal description » CK CSP-1 Block DiagramCSH LSI CSP-2 SP6012C-003 Signal Description HSY2 2BLK2 CSP 2 Block Diagram 3r00DSP2 OUT CAS OUT GDC Graphic display controller UPD7220 signal description AD15ILC2 NK-CLCAT~BTI CSR-1MAGE CG Address Select Circuit Structure Vsync Circuit description Character Vram select circuit Blsc Set GDC command code Read/write from the Z-80 to V-RAM Return when all parameters were sent Csrw C 49H -COMMAND CodeWrite C 23H Command Code Vecte C 6CH Command Code Fifo Empty? 60H ExplanationVECTE. Dot address is structured on the screen Following manner Dot display program example-1 P4 88H P5 HH I T E C 23HKind of line solid line Floppy disk Outline TJ ILJ n VnVn n nV nnn7 Ci D ci Ici Data MZ3500 MFD interface block diagram FDC UPD765 22 «- o Window UPD765 signal description Trigger motor on of the timer 555 Selects FDD MZ350CPort used in the MFD interface is as follows MFM recording method Controls during read, write, seek, and re- calibrate Media detection3500 Precompensate Circuit Control during seek and recalibration VFO circuit Purpose String of data Pulses from the FDD Data window VFO circuit configuration Filter Phase Detector Amplifier Window MFM Mode BQA FM mode timing chart \\\\ Aload Side =3DSC 76 iy 7 EH 77 / FFH \128Track 10 sector Indicates the byte position From the top of directory Ii Patat B144 6145 B146 B147 39 B148 B149 B150 B15139 B74 B75 1015 General specification Data transmission formatMZS500 Example 7-bits, even parity, 1 stop bit Start AC controlsOFF KTS MZ3500 Data output control8251 AC 3SOO RXEN,UTR , T X E N 200 9 6.3256 128 Wl -» «--N 8253 8253 OUT Printer interfacing circuit AA3DAT DS7 Output General description of the parallel interfaceData transfer timing I/O port map Clock circuit Schematic Read HoldWrite Hold SET DIN MZ3500 PD1990AC Block diagram LSB MSB Mmmil » GETE1 J 3500 S I CGP I/O SFD 1/F SW2 SW1 On on CE332P OFF on MZ1P02 On OFF IO2824 OFF OFF DipswaSEC FD2 \f Canbe in either state Functions Block diagramDescription of each block Switching regulator +5V Alarm generation circuit Timing chart At rrn Specification of keyboard controlKey Key search timing 2s 2s22 21Key Strobe 22.5/-s 132.5Protocol Key to sub CPU Keyboard controller basic flow Keyboard controller signal description XTAL1 XTAL2 Reset INTPIN ALE DBO DB7 GND On OFF Procedure Sub-CPU side Shared RAM CRT inter face testAbnormal S C I I 00-FF 1 5 c * O DR O.7 Abnormal test endingReady O.H ROM-IPL Main CPU Checker Flow Chart 1/2 Main CPU Checker Flow Chart M? 100 101 M7*500 Keyboard controller ROM test Keyboard test IPL Flow Chart Jump \ Boot Address System SEEK, Read ErrorError Load Iocs SEEK& Read SUB CPU IPL Flow Chart 105 LJ LJ LJ LJ LJ LJ LJ R R R R F1 LU LU U LJ LlJ LJ U U U J l J J L i J L L j l J J L l J L L l AIO IwCRoB MZ-35OO Parts Guide LI LED PWB No Parts CodeS C R I P T I O N IE--or Ooss-zw MZ-3500 Parts CodeN T K Qcnw Connector S C R I P T I O N MZ-3500 NO. Parts CodeParts Code A a N a D VH S N 7 4 0 6 N NEW Mark Rank Part S C R I P T I O NCoos J9, MZ1K02,1K03,1K04,1K05 Key unit M2-3500 SOC LSI RAMLA a NO. Parts Code D e Tin Parts Code N a a MZ-3500 Sharp Corporation