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Sharp MZ-3500 Ii Patat, B144 6145 B146 B147 39 B148 B149 B150 B151, 39 B74 B75, 1015, Block

Models: MZ-3500

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Page 63

MZ3500

oBlock number allocation

The program and data areas are located after Track 2 1 block = 2K bytes (8 sector)

		(Double side)				(Single sided)
		Block	No			Block	No
track		Front		Reverse	track	Front
		Front		Reverse		Front
2	BO	Bl	B2	B3	2	BO	Bl
3	B4	B5	B6	B7	3	B2	B3

I

38

B144

6145

B146 B147

39 B148 B149 B150 B151

2Kx 152 = 304K

Each track is blocked in the following manner:

1 sector	2	sec tor '
3	4
5	6
1 block		1 block
13	14
15 sector	16 sector

I

38 B72 B73

39 B74 B75

2KX 76=152K

oTrack 1, Sector 1 information (CP/M)

05

SECTO

AA TRACK SIDE SECTOR N ^1 NUM BER

t	t	. . . . . .
Drive unit
specification
Represents the		BOOT
system media	(•

1015

ii PATAT

ii *ANSF-TRACK SIDE SECTOR N

ER NU 1KAt*ii

MBER 1

Load address Start address

					20	50	51
		SECTO			SECTO		SECTO~		I
		R NUM TRACK			R NUM		R NUM	T?F%! \
		BER			BER		BER	j	j
								Indicates
							the end
					S U B - I O CS
. _ 0 Single density (front, Track 0)
1 Double density (other than front. Track 0)
SIDE =	0	Side 0		(front)
SIDE =	1	Side	1	(reverse)
	1	Side	1	(reverse)
Nosof data transfers			= INT		[IOCS capacity/1 K] + 1

•Sub IOCS can be divided into either blocks If divided to less than eight blocks, the block that follows

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Image 63

Sharp MZ-3500 service manual Ii Patat, B144 6145 B146 B147 39 B148 B149 B150 B151, 39 B74 B75, 1015, Block

Contents

Personal Computer Model Z-350 Video TimerBACKUP, INIT, COPY, DEBUG, Killall MemorySFDI/F Refer to the page TIN Circuit DiagramSlot Slot2 LSI, 1C CmosicChange Disp PresetSymbol SdispUser Basic Area RAMBase SystemMZ-1D07 MZ3500 System configuration of Model MS1 = D MSO = 0 L Software Memory ConfigurationTiming of Reset Signal ROM-IPL SD1 System Loading & CP/MBank Select FfffMAO ROM SD3 RAM based BasicOperational description BankMain Memory Mapper Block diagram Relation between MMR main memoryMain CPU and I/O port This paragraph discusses main CPU I/OTable below describes address map Sub CPU and I/O port 0001Main CPU \m MZ3500Coab Memory mapper MMRSP6102R-001 Block diagramTo Reset Address BUSMZ3500 Memory mapper MMR SP6102R-001 signal description RAS ROW Address Select Line Address Select SignalSrdy Pin No IN/OUT RO1BRO2B 1 1 1 1 1 1 FF 14 I N D3 A7 A6 A5A4A3A2AlAO H E X Uhus 1 O1 1 1 1 0 KI1 Dl Do 17 D6 D5 D2 Dl 1 1 1 1 1 0 FE do D4 D3MZ3500 Memory ROMIPL, RAMCOM, S-RAM select circuit CRT SpecificationAsci Summary of video display specificationGraphic dot Dot pitchBlue Dot color designated byCH AT KA7CH AI +,! AT A r + + G Ascii CG #1 FFFVideo RAM Structure of Vram Structure of character Vram When read/write from GDC #07FFA#0000 8bit Read/write by Z-80 via the GDC 640 x 200 dots display modeFV = 60 Hz 16KO signal switching 640 x 400 bits display mode FH = 20.92 kHz FV = 47.3 HzSetup of GCD master/slave Master/slave setup by combinationGraphic V-RAM Address Crtc block diagramPage Master slice LSI CSP-1 SP6102C 002 signal description CSP-1 Block Diagram » CKCSH HSY2 2BLK2 LSI CSP-2 SP6012C-003 Signal DescriptionCAS OUT CSP 2 Block Diagram3r00 DSP2 OUTGDC Graphic display controller UPD7220 signal description CSR-1MAGE AD15ILC2NK-CLC AT~BTIStructure CG Address Select CircuitCircuit description VsyncBlsc Character Vram select circuitRead/write from the Z-80 to V-RAM Set GDC command codeFifo Empty? Return when all parameters were sentCsrw C 49H -COMMAND Code Write C 23H Command Code Vecte C 6CH Command CodeFollowing manner Dot display program example-1 60HExplanation VECTE. Dot address is structured on the screenI T E C 23H P4 88H P5 HHKind of line solid line Outline Floppy diskTJ ILJ n Ci D ci Ici VnVn n nV nnn7Data MZ3500 MFD interface block diagram 22 «- o Window FDC UPD765UPD765 signal description MFM recording method Trigger motor on of the timer 555 Selects FDDMZ350C Port used in the MFD interface is as followsControl during seek and recalibration Controls during read, write, seek, and re- calibrateMedia detection 3500 Precompensate CircuitPurpose String of data Pulses from the FDD Data window VFO circuitFilter Phase Detector Amplifier Window VFO circuit configurationBQA MFM ModeFM mode timing chart \\\\ Side = Aload3DSC Indicates the byte position From the top of directory 76 iy 7 EH 77 / FFH\128 Track 10 sector1015 Ii PatatB144 6145 B146 B147 39 B148 B149 B150 B151 39 B74 B75Example 7-bits, even parity, 1 stop bit General specificationData transmission format MZS500AC controls StartOFF MZ3500 Data output control KTS8251 AC RXEN,UTR , T X E N 3SOO128 2009 6.3 256«--N Wl -»8253 OUT 8253DS7 Printer interfacing circuitAA3 DATGeneral description of the parallel interface OutputData transfer timing I/O port map DIN Clock circuit SchematicRead Hold Write Hold SETLSB MSB MZ3500 PD1990AC Block diagram» GETE1 J MmmilSFD 1/F 3500S I C GP I/OFD2 SW2 SW1 On on CE332P OFF on MZ1P02 On OFF IO2824 OFF OFFDipswa SEC\f Canbe in either state Block diagram FunctionsDescription of each block +5V Switching regulatorTiming chart Alarm generation circuitSpecification of keyboard control At rrnKey Strobe Key search timing2s 2s22 21 Key132.5 22.5/-sProtocol Key to sub CPU Keyboard controller basic flow ALE DBO DB7 GND Keyboard controller signal descriptionXTAL1 XTAL2 Reset INT PINOn OFF Sub-CPU side ProcedureS C I I 00-FF Shared RAMCRT inter face test AbnormalAbnormal test ending 1 5 c * O DR O.7Ready O.H ROM-IPL Main CPU Checker Flow Chart 1/2 100 Main CPU Checker Flow Chart M?M7*500 101Keyboard test Keyboard controller ROM testIPL Flow Chart Load Iocs SEEK& Read Jump \ Boot Address SystemSEEK, Read Error Error105 SUB CPU IPL Flow ChartR R R R F1 LJ LJ LJ LJ LJ LJ LJU J l J J L i J L L j l J J L l J L L l LU LU U LJ LlJ LJ U UIwC AIORoB MZ-35OO Parts Guide LI No Parts Code LED PWBS C R I P T I O N IE--or Ooss-zw Qcnw MZ-3500Parts Code N T KS C R I P T I O N ConnectorA a N a D MZ-3500NO. Parts Code Parts CodeNEW VH S N 7 4 0 6 NPart S C R I P T I O N Mark RankCoos M2-3500 J9, MZ1K02,1K03,1K04,1K05 Key unitNO. Parts Code SOCLSI RAM LA aD e Tin N a a Parts CodeMZ-3500 Sharp Corporation