Sharp MZ-3500 service manual GDC Graphic display controller UPD7220 signal description

M 7.3500

4-7. GDC (Graphic display controller) (UPD7220) signal description

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22-34

Polarity
Signal Name
2XCCLK	IN	Double character clock supplied from the external dot timing generator which has the followin^
		two modes:
		1. Character display mode1 Single phaseclock at one half of the one character wide cycle
		2. Graphic disp'ay mode: Single phase clock of eight dots that cycles
DBIN	OUT	Memory contro signal supp'ied to the image memory from the GDC, which causes the image
		memory output data to be sent on the data bus.

HSYNC-REF OUT Memory contro' signal sent to the image memory from the GDC, which is the horizontal synchronizing signal.

•Since the image drawing process is automatically interrupted in the dynamic RAM mode the refresh address is output during the HSYNC period. It can also be used as the refresh timing signal.

•Refresh is accomplished by suppressing the CAS signal derived from the RAS signal in the external circuit when the HSYC is at h gh lebel (Horizontal Synchronous - Refresh timing)

VSYNC	IN/OUT	Establishes one of following two modes, depending on whether the GDC is operated by the master
EX.SY		or the slave.
NC		1. When the master is operational: sends out the vertical synchronizing signal.

2.When the slave is operational : The synchronizing signal generationcounter is initialized by a high level input.

BLNK	OUT	Erase signal output is issued at the following times (blanking signal):
		1. Horizontal flyback	period.
		2. Vertical flyback period
		3. Period from the execution of the SYNC SET command to the execution of the DISP START
		command.
RAS	OUT	Memory control signal sent to the image memory from the GDC,
		• In the dynamic RAM mode, it is used asthe reference signal of RAS. When at high level, used
		as the timing signal by which the address signal is latched.
					(Row Address Strobe)
DRQ	OUT	DMA request output which is connected with the DRQ input of the DMA controller is output by the
(NO USE)		following two commands'
		1. DREQE (DMA request write): CPU memory to image memory.
		2. DREQR (DMA request read). Image memory to CPU memory.
		It will be continuously output until the DMA transfer word/byte number set by the VECTW (vector
		write) command becomes zero.			(DMA Request)
DACK	IN	Signal supplied from the DMA controller that is subsequently decoded by the GDC as the read or
(NO USE)		write signal during DMA.			(DMA Acknowledge)
RD	IN	In the external circuit RD is combined with the chip select signal (CS).And is used when the CPU
		reads from the GDC either data or status flag and the signal DACK.
					(Read strobe)
WR~	IN	In the external circuit WR is combined with the chip select signal. And is used when the CPU
		writes to the GDC either a command or parameter and the signal DACK.
					(Write strobe)
AO	IN	Normally, connected with the address line and is used TOdesignate data type.
		AO	RD	WR	function	^Mode^'
		0	0	1	READ STATUS FLAG	IN	#70	IN	#60
		1	0	1	READ DATA	IN	#71	IN	#61
		0	1	0	WRITE PARAMETER	OUT	#70	OUT	#60
		1	1	0	WRITE COMMAND	OUT	#71	OUT	#61

		GDC1	GDC2
		(Address Bus 0)
DBO-DB7	IN/OUT	Bidirectional data bus connected to the system bus.
		(Data Bus 0 - 7 )
GND	IN	0V supply.
LPEN	IN	Light pen strobe nput. When a input light is sensed by the light pen, it outputs a high level signal.
		The CPU can then read the display address via the LPENR (Light Pen Read) command.
ADO-AD12	IN/OUT	Bidn ectional address/data bus connected betweenthe image memory and the GDC on which address
		and data are sent on the bus by means of multiplexer ALE (Address Latch Enable) is drived from
		the RAS output in the exter nal circu t.

(Address/Data bus 0 - 12)