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M 7.3500
4-7. GDC (Graphic display controller) (UPD7220) signal description
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Signal Name |
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2XCCLK | IN | Double character clock supplied from the external dot timing generator which has the followin^ |
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| two modes: |
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| 1. Character display mode1 Single phaseclock at one half of the one character wide cycle |
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| 2. Graphic disp'ay mode: Single phase clock of eight dots that cycles |
DBIN | OUT | Memory contro signal supp'ied to the image memory from the GDC, which causes the image |
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| memory output data to be sent on the data bus. |
•Since the image drawing process is automatically interrupted in the dynamic RAM mode the refresh address is output during the HSYNC period. It can also be used as the refresh timing signal.
•Refresh is accomplished by suppressing the CAS signal derived from the RAS signal in the external circuit when the HSYC is at h gh lebel (Horizontal Synchronous - Refresh timing)
VSYNC | IN/OUT | Establishes one of following two modes, depending on whether the GDC is operated by the master |
EX.SY |
| or the slave. |
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| 1. When the master is operational: sends out the vertical synchronizing signal. |
2.When the slave is operational : The synchronizing signal generationcounter is initialized by a high level input.
BLNK | OUT | Erase signal output is issued at the following times (blanking signal): |
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| 1. Horizontal flyback | period. |
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| 2. Vertical flyback period |
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| 3. Period from the execution of the SYNC SET command to the execution of the DISP START | |||||||
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| command. |
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RAS | OUT | Memory control signal sent to the image memory from the GDC, |
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| • In the dynamic RAM mode, it is used asthe reference signal of RAS. When at high level, used | |||||||
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| as the timing signal by which the address signal is latched. |
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| (Row Address Strobe) |
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DRQ | OUT | DMA request output which is connected with the DRQ input of the DMA controller is output by the | |||||||
(NO USE) |
| following two commands' |
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| 1. DREQE (DMA request write): CPU memory to image memory. |
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| 2. DREQR (DMA request read). Image memory to CPU memory. |
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| It will be continuously output until the DMA transfer word/byte number set by the VECTW (vector | |||||||
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| write) command becomes zero. |
| (DMA Request) |
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DACK | IN | Signal supplied from the DMA controller that is subsequently decoded by the GDC as the read or | |||||||
(NO USE) |
| write signal during DMA. |
| (DMA Acknowledge) |
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RD | IN | In the external circuit RD is combined with the chip select signal (CS).And is used when the CPU | |||||||
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| reads from the GDC either data or status flag and the signal DACK. |
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| (Read strobe) |
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WR~ | IN | In the external circuit WR is combined with the chip select signal. And is used when the CPU | |||||||
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| writes to the GDC either a command or parameter and the signal DACK. |
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| (Write strobe) |
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AO | IN | Normally, connected with the address line and is used TOdesignate data type. |
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| AO | RD | WR | function | ^Mode^' |
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| 0 | 0 | 1 | READ STATUS FLAG | IN | #70 | IN | #60 |
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| 1 | 0 | 1 | READ DATA | IN | #71 | IN | #61 |
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| 0 | 1 | 0 | WRITE PARAMETER | OUT | #70 | OUT | #60 |
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| 1 | 1 | 0 | WRITE COMMAND | OUT | #71 | OUT | #61 |
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| GDC1 | GDC2 |
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| (Address Bus 0) |
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| IN/OUT | Bidirectional data bus connected to the system bus. |
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| (Data Bus 0 - 7 ) |
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GND | IN | 0V supply. |
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LPEN | IN | Light pen strobe nput. When a input light is sensed by the light pen, it outputs a high level signal. | |
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| The CPU can then read the display address via the LPENR (Light Pen Read) command. | |
| IN/OUT | Bidn ectional address/data bus connected betweenthe image memory and the GDC on which address | |
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| and data are sent on the bus by means of multiplexer ALE (Address Latch Enable) is drived from | |
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| the RAS output in the exter nal circu t. |
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(Address/Data bus 0 - 12)