F Canbe in either state | Sharp MZ-3500 guide

MZ3500

DIP SW(A)DIPSW(B)

OFF OFF OFF ON ON ON

ON OFF OFF ON ON ON

OFF OFF ON ON ON ON

ON OFF ON ON ON ON

OFF ON ON ON ON ON

ON ON ON ON ON ON

X ><^ OFF OFF OFF

\(f Canbe in either state

•

Switches are set in this manner before shipment of machines this us the single-sided minifloppy disk drive.

Switches areset in this manner before shipment of	, My-it^n Pn^41
machines that usethe double-sided minifloppy	( 11/171540' vv"=/n
disk drive.	' '

Switches are set in this manner when the SH is used for the optional MFD

Switches are set in this manner when the DH is used for the optional MFD

Test mode *1

Test mode "2

Individual CPU PWB test

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Page 79

Image 79

Sharp MZ-3500 service manual f Canbe in either state

Contents

Personal Computer Model Z-350 Video TimerBACKUP, INIT, COPY, DEBUG, Killall Memory SFDI/F Refer to the page TIN Circuit DiagramSlot Slot2 LSI, 1C Cmosic Change Disp PresetSymbol Sdisp User Basic Area RAMBase System MZ-1D07 MZ3500 System configuration of Model MS1 = D MSO = 0 L Software Memory Configuration Timing of Reset Signal ROM-IPL SD1 System Loading & CP/M Ffff Bank SelectMAO ROM SD3 RAM based BasicOperational description Bank Main Memory Mapper Block diagram Relation between MMR main memory This paragraph discusses main CPU I/O Main CPU and I/O portTable below describes address map Sub CPU and I/O port 0001Main CPU \m MZ3500 Coab Memory mapper MMRSP6102R-001 Block diagramTo Reset Address BUS RAS ROW Address Select Line Address Select Signal MZ3500 Memory mapper MMR SP6102R-001 signal descriptionSrdy Pin No RO1B IN/OUTRO2B 1 1 1 1 1 1 FF 14 I N D3 A7 A6 A5A4A3A2AlAO H E X Uhus 1 O1 1 1 1 0 KI1 Dl Do 17 D6 D5 D2 Dl 1 1 1 1 1 0 FE do D4 D3 MZ3500 Memory ROMIPL, RAMCOM, S-RAM select circuit CRT Specification Asci Summary of video display specification Graphic dot Dot pitchBlue Dot color designated by KA7 CH ATCH AI +,! AT A r + + G Ascii CG #1 FFF Video RAM Structure of Vram #07FFA Structure of character Vram When read/write from GDC#0000 8bit Read/write by Z-80 via the GDC 640 x 200 dots display mode FV = 60 Hz 16K O signal switching 640 x 400 bits display mode FH = 20.92 kHz FV = 47.3 HzSetup of GCD master/slave Master/slave setup by combination Graphic V-RAM Address Crtc block diagramPage Master slice LSI CSP-1 SP6102C 002 signal description » CK CSP-1 Block DiagramCSH HSY2 2BLK2 LSI CSP-2 SP6012C-003 Signal Description CAS OUT CSP 2 Block Diagram3r00 DSP2 OUT GDC Graphic display controller UPD7220 signal description CSR-1MAGE AD15ILC2NK-CLC AT~BTI Structure CG Address Select Circuit Circuit description Vsync Blsc Character Vram select circuit Read/write from the Z-80 to V-RAM Set GDC command code Fifo Empty? Return when all parameters were sentCsrw C 49H -COMMAND Code Write C 23H Command Code Vecte C 6CH Command Code Following manner Dot display program example-1 60HExplanation VECTE. Dot address is structured on the screen P4 88H P5 HH I T E C 23HKind of line solid line Outline Floppy disk TJ ILJ n Ci D ci Ici VnVn n nV nnn7 Data MZ3500 MFD interface block diagram 22 «- o Window FDC UPD765 UPD765 signal description MFM recording method Trigger motor on of the timer 555 Selects FDDMZ350C Port used in the MFD interface is as follows Control during seek and recalibration Controls during read, write, seek, and re- calibrateMedia detection 3500 Precompensate Circuit Purpose String of data Pulses from the FDD Data window VFO circuit Filter Phase Detector Amplifier Window VFO circuit configuration BQA MFM Mode FM mode timing chart \\\\ Aload Side =3DSC Indicates the byte position From the top of directory 76 iy 7 EH 77 / FFH\128 Track 10 sector 1015 Ii PatatB144 6145 B146 B147 39 B148 B149 B150 B151 39 B74 B75 Example 7-bits, even parity, 1 stop bit General specificationData transmission format MZS500 Start AC controlsOFF KTS MZ3500 Data output control8251 AC RXEN,UTR , T X E N 3SOO 128 2009 6.3 256 «--N Wl -» 8253 OUT 8253 DS7 Printer interfacing circuitAA3 DAT Output General description of the parallel interfaceData transfer timing I/O port map DIN Clock circuit SchematicRead Hold Write Hold SET LSB MSB MZ3500 PD1990AC Block diagram » GETE1 J Mmmil SFD 1/F 3500S I C GP I/O FD2 SW2 SW1 On on CE332P OFF on MZ1P02 On OFF IO2824 OFF OFFDipswa SEC \f Canbe in either state Functions Block diagramDescription of each block +5V Switching regulator Timing chart Alarm generation circuit At rrn Specification of keyboard controlKey Strobe Key search timing2s 2s22 21 Key 22.5/-s 132.5Protocol Key to sub CPU Keyboard controller basic flow ALE DBO DB7 GND Keyboard controller signal descriptionXTAL1 XTAL2 Reset INT PIN On OFF Sub-CPU side Procedure S C I I 00-FF Shared RAMCRT inter face test Abnormal 1 5 c * O DR O.7 Abnormal test endingReady O.H ROM-IPL Main CPU Checker Flow Chart 1/2 100 Main CPU Checker Flow Chart M? M7*500 101 Keyboard test Keyboard controller ROM test IPL Flow Chart Load Iocs SEEK& Read Jump \ Boot Address SystemSEEK, Read Error Error 105 SUB CPU IPL Flow Chart R R R R F1 LJ LJ LJ LJ LJ LJ LJ U J l J J L i J L L j l J J L l J L L l LU LU U LJ LlJ LJ U U AIO IwCRoB MZ-35OO Parts Guide LI LED PWB No Parts CodeS C R I P T I O N IE--or Ooss-zw Qcnw MZ-3500Parts Code N T K S C R I P T I O N Connector A a N a D MZ-3500NO. Parts Code Parts Code NEW VH S N 7 4 0 6 N Mark Rank Part S C R I P T I O NCoos M2-3500 J9, MZ1K02,1K03,1K04,1K05 Key unit NO. Parts Code SOCLSI RAM LA a D e Tin N a a Parts Code MZ-3500 Sharp Corporation