SUB CPU IPL Flow Chart, 105 | Sharp MZ-3500 specs

122. SUB CPU IPL FLOW CHART

( POWER ON A

SUB CPU IPL J

T,m«,

1

In t,alize8255

AMode 0.8 Mode 1.

C OUT

1

SUB CPU READY OFF

1

Rest GDC

1

Check ROM sum

Initialize GDC and check G VRAM

Set the custom LSI CSPI and

CSP2 control boards

Initialize GDCagatr

C-GDC, G-GDC command transfer

MZ-3500

IPL ROM is

broke u indicated on display

HALT	\
CUP STOP	I

- 105 -

Image 98

Sharp MZ-3500 service manual SUB CPU IPL Flow Chart, 105

Contents

Personal Computer Model Z-350 Memory TimerBACKUP, INIT, COPY, DEBUG, Killall Video LSI, 1C Cmosic Refer to the page TIN Circuit DiagramSlot Slot2 SFDI/F Sdisp PresetSymbol Change Disp System Basic Area RAMBase User MZ-1D07 MZ3500 System configuration of Model Software Memory Configuration MS1 = D MSO = 0 L Timing of Reset Signal SD1 System Loading & CP/M ROM-IPL MAO Bank SelectFfff Bank SD3 RAM based BasicOperational description ROM Block diagram Relation between MMR main memory Main Memory Mapper Table below describes address map Main CPU and I/O portThis paragraph discusses main CPU I/O MZ3500 0001Main CPU \m Sub CPU and I/O port Address BUS Memory mapper MMRSP6102R-001 Block diagramTo Reset Coab Srdy MZ3500 Memory mapper MMR SP6102R-001 signal descriptionRAS ROW Address Select Line Address Select Signal Pin No RO2B IN/OUTRO1B D2 Dl 1 1 1 1 1 0 FE do D4 D3 A7 A6 A5A4A3A2AlAO H E X Uhus 1 O1 1 1 1 0 KI1 Dl Do 17 D6 D5 1 1 1 1 1 1 FF 14 I N D3 MZ3500 Memory ROMIPL, RAMCOM, S-RAM select circuit Specification CRT Summary of video display specification Asci Dot color designated by Dot pitchBlue Graphic dot CH AI +,! AT A r + + G CH ATKA7 #1 FFF Ascii CG Video RAM Structure of Vram #0000 Structure of character Vram When read/write from GDC#07FFA Read/write by Z-80 via the GDC 640 x 200 dots display mode 8bit 16K FV = 60 Hz Master/slave setup by combination 640 x 400 bits display mode FH = 20.92 kHz FV = 47.3 HzSetup of GCD master/slave O signal switching Crtc block diagram Graphic V-RAM AddressPage Master slice LSI CSP-1 SP6102C 002 signal description CSH CSP-1 Block Diagram» CK LSI CSP-2 SP6012C-003 Signal Description HSY2 2BLK2 DSP2 OUT CSP 2 Block Diagram3r00 CAS OUT GDC Graphic display controller UPD7220 signal description AT~BTI AD15ILC2NK-CLC CSR-1MAGE CG Address Select Circuit Structure Vsync Circuit description Character Vram select circuit Blsc Set GDC command code Read/write from the Z-80 to V-RAM Write C 23H Command Code Vecte C 6CH Command Code Return when all parameters were sentCsrw C 49H -COMMAND Code Fifo Empty? VECTE. Dot address is structured on the screen 60HExplanation Following manner Dot display program example-1 Kind of line solid line I T E C 23HP4 88H P5 HH Floppy disk Outline TJ ILJ n VnVn n nV nnn7 Ci D ci Ici Data MZ3500 MFD interface block diagram FDC UPD765 22 «- o Window UPD765 signal description Port used in the MFD interface is as follows Trigger motor on of the timer 555 Selects FDDMZ350C MFM recording method 3500 Precompensate Circuit Controls during read, write, seek, and re- calibrateMedia detection Control during seek and recalibration VFO circuit Purpose String of data Pulses from the FDD Data window VFO circuit configuration Filter Phase Detector Amplifier Window MFM Mode BQA FM mode timing chart \\\\ 3DSC Side =Aload Track 10 sector 76 iy 7 EH 77 / FFH\128 Indicates the byte position From the top of directory 39 B74 B75 Ii PatatB144 6145 B146 B147 39 B148 B149 B150 B151 1015 MZS500 General specificationData transmission format Example 7-bits, even parity, 1 stop bit OFF AC controlsStart 8251 AC MZ3500 Data output controlKTS 3SOO RXEN,UTR , T X E N 256 2009 6.3 128 Wl -» «--N 8253 8253 OUT DAT Printer interfacing circuitAA3 DS7 Data transfer timing General description of the parallel interfaceOutput I/O port map Write Hold SET Clock circuit SchematicRead Hold DIN MZ3500 PD1990AC Block diagram LSB MSB Mmmil » GETE1 J GP I/O 3500S I C SFD 1/F SEC SW2 SW1 On on CE332P OFF on MZ1P02 On OFF IO2824 OFF OFFDipswa FD2 \f Canbe in either state Description of each block Block diagramFunctions Switching regulator +5V Alarm generation circuit Timing chart Key Specification of keyboard controlAt rrn Key Key search timing2s 2s22 21 Strobe Protocol Key to sub CPU 132.522.5/-s Keyboard controller basic flow PIN Keyboard controller signal descriptionXTAL1 XTAL2 Reset INT ALE DBO DB7 GND On OFF Procedure Sub-CPU side Abnormal Shared RAMCRT inter face test S C I I 00-FF Ready O.H Abnormal test ending1 5 c * O DR O.7 ROM-IPL Main CPU Checker Flow Chart 1/2 Main CPU Checker Flow Chart M? 100 101 M7*500 Keyboard controller ROM test Keyboard test IPL Flow Chart Error Jump \ Boot Address SystemSEEK, Read Error Load Iocs SEEK& Read SUB CPU IPL Flow Chart 105 LJ LJ LJ LJ LJ LJ LJ R R R R F1 LU LU U LJ LlJ LJ U U U J l J J L i J L L j l J J L l J L L l RoB IwCAIO MZ-35OO Parts Guide LI S C R I P T I O N No Parts CodeLED PWB IE--or Ooss-zw N T K MZ-3500Parts Code Qcnw Connector S C R I P T I O N Parts Code MZ-3500NO. Parts Code A a N a D VH S N 7 4 0 6 N NEW Coos Part S C R I P T I O NMark Rank J9, MZ1K02,1K03,1K04,1K05 Key unit M2-3500 LA a SOCLSI RAM NO. Parts Code D e Tin Parts Code N a a MZ-3500 Sharp Corporation