Silicon Laboratories SI2494/39, SI2493/57/34/15/04 TSSOP-24 SPI-Interface Clock-Frequency Options

AN93

2.1.4.3.Reset Strapping Options for TSSOP with SPI-Interface Table 8 lists the SPI-interface options for the 24-pin TSSOP package.

Table 8. TSSOP-24 SPI-Interface Clock-Frequency Options

Mode					Reset-Strap Pins
Input Clock	Three-Wire		Pin 4	Pin 9, RXD		Pin 16	Pin 17	Pin 23
	EEPROM		FSYNC	Pin 11, SCLK		INT	RI	DCD
	Interface?			Pin 15, AOUT
				Pin 18, SDI/EESD
32 kHz	No	1		1		0	1	1
	Yes	0		1		0	1	1
4.9152 MHz	No	1		1		0	0	X
	Yes	0		1		0	0	X
27 MHz	No	1		1		0	1	0
	Yes	0		1		0	1	0

2.1.5. Reset Strapping Options for QFN Parts

2.1.5.1.Reset Strapping Options for QFN Parts with UART Operation Table 9 lists the reset strapping options for QFN parts with UART operation.

Table 9. Reset Strapping Options for QFN Parts with UART Operation

Input Clk	Auto-Baud	Three-Wire				AOUT	EECLK					SDI
			FSYNCH		CTS				INT		RI			DCD
	Disable	EEPROM
		Interface
			Pin 2	Pin 21		Pin 15	Pin 13	Pin 35		Pin 19		Pin 8	Pin 28
32 kHz	No	No	1	1		1	1	1		1		1	1
		Yes	0	1		1	1	1		1		1	1
	Yes	No	1	1		1	1	1		1		0	1
		Yes	0	1		1	1	1		1		0	1
4.9152 MHz	No	No	1	1		1	1	1		0		1		X
		Yes	0	1		1	1	1		0		1		X
	Yes	No	1	1		1	1	1		0		0		X
		Yes	0	1		1	1	1		0		0		X
27 MHz	No	No	1	1		1	1	1		1		1	0
		Yes	0	1		1	1	1		1		1	0
	Yes	No	1	1		1	1	1		1		0	0
		Yes	0	1		1	1	1		1		0	0

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