Silicon Laboratories SI2494/39, SI2493/57/34/15/04 Layout Checklist, ISOmodem Layout Check List

AN93

11

11

C27			C26
	Y1
1		2

11

8D

1

Traces, pad sites and vias

U1 Si24HS

enclosed in box are in the DAA

3A

4C

5

section, and must be separated

1

XTALI

from all other circuits by 5 mm.

2

XTALO

C52 12

C7

C50

21

9C

Q5

VDD3.3

12

5

20

4B

VDD3.3

GND

6

19

R9

GND

VDDB

C53

7

VDDA

12

2

4A

3A

4D

8D

C51

R12*

C1

3B

+

R2

12

C1A

14

C4

1

QE

DCT2

16

6

13

3C

3E C2

2

15

Q4

C1B

DCT

IGND

3

RX

DCT3

14

4

IB

QB

13

R13*

5

C1B

QE2

12

6

11

C2B

SC

2

7

10

VREG

VREG2

8

9

*Note: Do

NOT

use ferrite

RNG1

RNG2

C5

3E

3E

C6

beads in place of R12 and

4G

R7

9B

4F

4E

R13.

4F

U2

Si3018

R8

9C

9C

C3

9A

3E

8C

10

RING

D1

FB2

R16

-

+

7A

RV1

3E

10

TIP

FB1

R15

C9

C8

7B

7B

7C

7C

7B

2

2

Note: Encircled references are described in the numbered paragraphs in Appendix A.

This is not a complete schematic. Only critical component placement and nets are drawn.

Figure 21. Illustrated Layout Guidelines

4.4.1. ISOmodem Layout Check List

Table 34 is a checklist that the designer can use during the layout process to ensure that all the recommendations in this application note have been implemented. Additionally, Figure 21 provides an annotated diagram of all relevant layout guidelines for the SI3054 CNR/AMR/ACR applications. See "10.4.2. Safety" on page 254 for information about design for safety compliance.

Table 34. Layout Checklist

P	#	Layout Items	Required
	1	U1 and U2 are placed so that pins 9–16 of U1 are facing pins 1–8 of U2. C1 and C2
		are placed directly between U1 and U2.
	2	Place U1, U2, C1, and C2 so that the recommended minimum creepage spacing for
		the target application is implemented. R12 and R13 should be close to U1.
	3	C1 and C2 should be placed directly between U1 and U2. Short, direct traces should
		be used to connect C1 and C2 to U1 and U2. These traces should not be longer than
		two inches and should be minimized in length. Place C2 such that its accompanying
		trace to the C2B pin (pin 6) on the Si3018 is not close to the trace from R7 to the
		RNG1 pin on the Si3018 (pin 8).
	4	Place R7 and R8 as close as possible to the RNG1 and RNG2 pins (pins 8 and 9),
		ensuring a minimum trace length from the RNG1 or RNG2 pin to the R7 or R8 resistor.
		In order to space the R7 component further from the trace from C2 to the C2B pin, it is
		acceptable to orient it 90 degrees relative to the RNG1 pin (pin 8).

Rev. 1.3 51