SUPER MICRO Computer X6QTE+, X6QT8 Chipset Overview, E8501 Chipset, Independent Memory Interface

X6QT8/X6QTE+ User's Manual

1-2 Chipset Overview

The E8501 Chipset

Built upon the functionality and the capability of the E8501 chipset, the X6QT8/ X6QTE+ motherboard provides the performance and feature set required for 4-Way servers with confi guration options optimized for communications, storage, computa- tion or database applications. The Intel E8501 chipset is built around the E8501 chipset North Bridge (NB), and the Intel E8501 chipset external Bridge (XMB).

The E8501 chipset North Bridge (NB) provides the interconnection between 64-bit Intel Xeon MP/7000 Series/7100 Series Processors, XMB (via four independent Memory Interfaces), I/O components via PCI-Express Links and ICH5R. It sup- ports up to four 64-bit Xeon processor MP/7000 Series/7100 Series processors at a Front Side Bus of 667MHz or 800MHz. It offers ECC protection on data signals, parity protection on address signals, and supports Return Data by Enhanced Defer to allow for extraordinary completion.

Independent Memory Interface

Memory support features include the following:

•Four Independent Memory Interface (IMI) ports, each with up to 5.33 GB bandwidth (read) and 2.67 GB bandwidth (write) simultaneously at 166.7 MHz, or with up to 6.4 GB bandwidth (read) and 3.2 GB bandwidth (write) simulta- neously at 200 MHz

•40-bit addressing support provides one terabyte addressing capability

•Memory technology independent

I/O Interfaces

The E8501 chipset relies on PCI Express to provide the interconnection between the North Bridge and the I/O subsystem. The I/O subsystem is based on three x4 PCI Express links, two x8 PCI Express links, and one HI1.5 link.

•Three x4 and two x8 (each can be confi gured as two x4,) making a total of seven x4 links

•Dual PXH Controllers with 2 PCI-X buses per controller. (Each bus supports up to 133 MHz.) (*Note: for the X6QT8 only.)

HI 1.5

•8-bit wide, 4x data transfer, 66 MHz base clock with 266 MB/s bandwidth

•Legacy I/O interconnection to the ICH5R

Transaction Processing Capabilities

•64 transactions processed concurrently

•128-entry Common Data Cache (CDC) for write combining and write buffering

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