Texas Instruments TCM4300 - page 41

4–6

delay after the last symbol occurs (2 SINT periods before TXGO goes low); then the transmit outputs decay

to zero differential voltage (each output at the voltage supplied to the VCM input terminal). The shape of the

decay is the transient resulting from the internal SQRC filtering. The transmit outputs are held at zero

differential voltage 6 SINT periods (3 symbol periods) after the start of the decay. At this time the PAEN digital

output is set low (see Figure 4–1 and Figure 4–2).

Nonzero values of the BST offset register increase the delays of both the transmit waveforms and PAEN

relative to the edges of TXGO after it is internally sampled by SINT. The delays are increased in increments

of 1/4 SINT (1/8 symbol period).

For delays of 1 SINT or greater, the fractional part of the delay can be achieved using the BST offset register

with the remaining integer SINT delay implemented externally by delaying the writing to TXGO and TXI.

The relative timing of PAEN and the transmit waveforms is not affected by the BST offset register.

The IS-54 standard describes shortened bursts and normal bursts. The two types differ in duration and

number of transmitted bursts, burst length being determined by the TXGO bit.

First MEP Last MEP

>>> >>>

>>>

SINT

TXGO

TXI data bit

PAEN

TXI/Q output ramp

Input Bits

Dibit transmission

†Total delay = d (SINT/4 or T/8) where d = integer value (0,1,2,3) written to the BST offset register.

6 SINT Periods

d(T/8)†

9.5 SINT Periods

N+3 SINT Periods

(N = Total number of bits sent)

15.5 SINT Periods +d(T/8)

>>>

19.5 SINT Periods +d(T/8)

Figure 4–1. Power Ramp-Up/Ramp-Down TIming Diagram

Contents

Main Page Page Page Contents Section Title Page Page List of Illustrations Figure Title Page List of Tables Table Title Page 1 Introduction 1.1 Features 12 1.2 TCM4300 Functional Block Diagram 1.3 Pin Assignments 1.4 Terminal Functions Page Page Page 2 Electrical Specifications 2.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless otherwise noted) 2.2 Dissipation Rating Table 2.3 Recommended Operating Conditions 2.4 Electrical Characteristics Over Full Range Of Operating Conditions (Unless Otherwise Noted) 2.4.1 Power Consumption 2.4.2 Reference Characteristics 2.4.3 Terminal Impedance 2.4.4 RXIP, RXIN, RXQP, and RXQN Inputs (AVDD = 3 V, 4.5 V, 5 V) 2.4.5 Transmit I and Q Channel Outputs 2.4.6 Auxiliary D/A Converters 2.4.7 Auxiliary D/A Converters Slope (AGC, AFC, PWRCONT) 2.4.8 Auxiliary D/A Converters Slope (LCDCONTR) 2.4.9 RSSI/Battery A/D Converter 2.5 Operating Characteristics Over Full Range of Operating Conditions (Unless Otherwise Noted) 2.5.1 Receive (RX) Channel Frequency Response (RXI, RXQ Input in Digital Mode) 2.5.2 Receive (RX) Channel Frequency Response (FM Input in Analog Mode) 2.5.3 Transmit (TX) Channel Frequency Response (Digital Mode) 2.5.4 Transmit (TX) Channel Frequency Response (Analog Mode) Page 3 Parameter Measurement Information 3.1 MCLKOUT Timing Requirements (see Figure 31 and Note 1) Page Page Page Page Page Page Page Page 3.10 Switching Characteristics, TCM4300 to DSP Interface (Read Cycle) (see Figure 310) Figure 310. TCM4300 to DSP Interface (Read Cycle) 3.11 Switching Characteristics, TCM4300 to DSP Interface (Write Cycle) (see Figure 311) Figure 311. TCM4300 to DSP Interface (Write Cycle) Page 4 Principles of Operation 4.1 Data Transfer 4.2 Receive Section Table 42. RXIP, RXIN, RXQP, and RXQN Inputs (AVDD = 3 V, 4.5 V, 5 V) 4.3 Transmit Section Modulation error percentage 100 |e| |s| % 4.4 Transmit Burst Operation (Digital Mode) Page 4.5 Transmit I And Q Output Level 4.6 Wide-Band Data Demodulator 4.7 Wide-band Data Interrupts 4.8 Wide-band Data Demodulator General Information 4.9 Auxiliary DACs, LCD Contrast Converter 4.9 Auxiliary DACs, LCD Contrast Converter (continued) 4.10 RSSI, Battery Monitor 4.11 Timing And Clock Generation 4.11.1 Clock Generation 4.11.2 Speech-Codec Clock Generation MCLKIN 4.11.3 Microcontroller Clock 4.11.4 Sample Interrupt SINT 4.11.5 Phase-Adjustment Strategy Figure 45. Timing and Clock Generation for 38.88-MHz Clock 4.12 Frequency Synthesizer Interface Figure 46. Synthesizer Interface Circuit Block Diagram Page 4.13 Power Control Port Page 4.14 Microcontroller-DSP Communications 421 4.15 Microcontroller Register Map Table 417. Microcontroller Register Definitions 4.16 Wide-Band Data/Control Register 4.17 Microcontroller Status and Control Registers Table 419. MStatCtrl Register Bits 4.18 LCD Contrast 4.19 DSP Register Map Table 421. DSP Register Definitions Figure 411. DSP Interface 4.20 Wide-Band Data Registers Bit 9 of the wide-band data register is the most recently received bit as shown below. 4 4.21 Base Station Offset Register The delay in the TCM4300 TX channels is increased by the amount: BST OFFSET dTSINT 4.22 DSP Status and Control Registers 4.23 Reset 4.23.1 Power-On Reset 4.23.2 Internal Reset State 4.24 Microcontroller Interface 4.24.1 Intel Microcontroller Mode Of Operation 4.24.2 Mitsubishi Microcontroller Mode of Operation 4.24.3 Motorola Microcontroller Mode of Operation Table 428. Microcontroller Interface Connections for Motorola Mode (16 bits) Page 5 Mechanical Data 5.1