Texas Instruments TCM4300 manual LCD Contrast, ±19. MStatCtrl Register Bits, Ldc D/A, Lcden

Table 4±19. MStatCtrl Register Bits

BIT	R / W	NAME	FUNCTION	RESET VALUE
			Synthesizer out of lock. SYNOL is equal to the level applied to SYNOL
			input pin. SYNOL can be used as an input for an externally generated	Level on
7	R	SYNOL	status signal to prevent transmission when external synthesizers are	SYNOL input
			out of lock. In digital mode, when SYNOL is high, PAEN is not asserted	terminals
			and no signal can be transmitted from TXIP, TXIN, TXQP, and TXQN.
			Transmitter on indicator. TXONIND is equal to the level applied to	Level for
6	R	TXONIND	TXONIND, and it can indicate that power is applied to the power	TXONIND input
			amplifier.	terminals
			Synthesizer interface ready. SYNRDY indicates that frequency
5	R	SYNRDY	synthesizer is ready to be programmed by the microcontroller. When	1
			SYNRDY is 1, the microcontroller can program the frequency
			synthesizer interface; a 0 indicates the interface circuit is busy.
			MCLKOUT enable. When MCLKEN is set to 1 by the microcontroller,
4	R / W	MCLKEN	the 38.88-MHz master clock is output at MCLKOUT. Writing 0 to	1
			MCLKEN disables MCLKOUT.
			Conversion ready. A 1 indicates that the latest RSSI or battery voltage
3	R	CVRDY	A/D conversion is complete and can be read from the RSSI or battery	1
			register location. CVRDY goes to 0 when the microcontroller reads from
			either of these locations.
2		AuxFS[1]	Auxiliary DACs full-scale select. The auxiliary DACs are AGC, AFC,	0
			PWRCONT and also LCD CONTR DAC. The microcontroller selects
	R / W
1		AuxFS[0]	the full-scale output ranges with these bits (see Table 4±11 and	0
			Table 4±12 for bit-to-output range mapping).
0	R / W	MPAEN	Microcontroller PA enable. A 0 indicates that the external PA enable line	0
			PAEN is prevented from going active (see Figure 4±9).

TXI Offset and TXQ Offset: These registers allow the differential offset voltages TXIP ± TXIN and TXQP ± TXQN to be adjusted to compensate for internal and/or external offsets. The magnitude of adjustment is D ⋅step size, where D is a 6-bit, 2s-complement integer written into bits 5±0 of these registers, as shown here:

	7 ± 6	5 ± 0
TXI(Q) Offset
	Reserved	TXI(Q) Offset Value
		W

4.18 LCD Contrast

The LCD contrast register allows for 16 levels of control of terminal LCD contrast. The register is input to the LCD contrast D/A converter allowing control of the level of intensity of the LCD display as shown here:

	7 ± 4	3 ± 1	0
LDC D/A	LCD Contrast	Reserved	LCDEN
			(active low)
	W		W

4±24