TCM4300 Functional Block Diagram | Texas Instruments manual

1.2TCM4300 Functional Block Diagram

TXIP

TXIN

TXQP

TXQN

RXIP

RXIN

RXQN

RXQP

FM

AGC

AFC

PWRCONT

PAEN

OUT1

FMRXEN IQRXEN TXEN SCEN SYNOL TXONIND

SYNCLK

SYNDTA

SYNLE [2:0]

RSSI

BAT

LCDCONTR

Low-		Digital Filter		A		TXI (04b)
Low-
Pass	D/A		I
Pass	D/A	Analog	I	D
Filter		Analog			π/4 Shifted
Filter		Mode (LPF)
		Mode (LPF)				TX Data
					DQPSK	TX Data
				A	DQPSK	Registers
Low-				A	Modulation	Registers
Low-		Digital			Modulation
Pass	D/A	Digital	Q	D			10
Filter	D/A	Mode (SQRC)	Q	D
Filter		Mode (SQRC)				TXQ (05b)
						TXQ (05b)
0Fh	TX		6		ModeSel
0Fh	TX		6			DSP
10h	Offset					DSP
10h	Offset					Interface
						Interface
Anti-		Digital Filter	RXI	02h		Control	3
Anti-	A/D	Digital Filter	RXI	02h		Control	CONTROL
aliasing	A/D	Analog			10		10
Filter		Analog			10	Data	10
Filter		Mode (LPF)	Sample		10	Data	DATA
		Mode (LPF)
							4
			Register				4
Anti-			Register			Address	ADDRESS
						Address	ADDRESS
		Digital
aliasing	A/D	Digital
aliasing	A/D	Mode (SQRC)
Filter		Mode (SQRC)	RXQ	03h
Filter			RXQ	03h

	Low-	Wide-band						Internal		Power On	RSINL
	Low-	Wide-band		WBD	00h	8		RESET		RESET	RSINL
	Pass	Data		Register	00h
	Filter	Demodulator				5					RSOUTH
				WBD	01h	5					RSOUTL
				WBD	01h	5					SINT
				Control	00h	5					SINT
			Internal	Control	00h						MCCLK
											MCCLK
		AUX									CSCLK
			Clocks	Clock							CSCLK
			Clocks								CMCLK
		D/As									CMCLK
	8	D/As		Generation
	8			Generation							XTAL
	D/A	09h(D)		and					Clock		XTAL
	D/A	09h(D)					38.88MHz		Clock		MCLKIN
							38.88MHz		Oscillator		MCLKIN
				Timing					Oscillator		MCLKOUT
				Timing							MCLKOUT
	8			Adjustment		8			TX
	8			Logic
	D/A	0Ah(D)		Logic							VCM
	D/A	0Ah(D)						Common Mode Input

		Control
		Control
	8	Registers	7						Bias		RBIAS
	8		8						Control		RBIAS
	D/A	0Bh(D)	8						Control
	D/A	0Bh(D)
				10			Vref			Ref
			0Ch	10						Ref	VHR
			0Ch							Gen	VHR
		DStatCtrl								Gen
		DStatCtrl				8
		Register				8	10				REFCAP
	Power	Register					10				REFCAP
	Power
	Control			8							MWBDFINT
			0Eh	8
			0Eh
		MStatCtrl									DWBDINT
		Register									DWBDINT
		Register									CINT
											CINT
											DINT
					06h	8	8		06h	DSP to
			Microcontroller		06h				06h	DSP to
			Microcontroller						Microcontroller
			to DSP FIFO			8	8		Microcontroller
			to DSP FIFO		01h	8	8		01h	FIFO
					01h				01h	FIFO
	Synthesizer			8
	Interface			8
	Interface
3	03h ± 09h								Micro-
3									Micro-
				RSSI				controller
				RSSI				Interface		6
		A/D		0Bh	8			Control		6	CONTROL
								Control			CONTROL
				BAT			8			8
				BAT
				0Ch					Data		DATA
				0Ch					Data		DATA
								Address		5	ADDRESS
			4	LCD	4			Address			ADDRESS
		D/A	4	LCD	4
		D/A		0Dh
				0Dh

1±2

Image 10

Texas Instruments manual TCM4300 Functional Block Diagram

Contents

Data Manual SLWS010F TCM4300 Data Manual Important Notice Contents Mechanical Data ±1 List of Illustrations List of Tables Features Introduction TCM4300 Functional Block Diagram VSS Pin AssignmentsPZ Package TOP View Fmrxen Terminal Functions Terminal Description Name Dvdd DsprwDspstrbl Dvss Mclkin McdsMTS1 Mcrw Synclk ScenSint Syndta Package Power Rating Above TA = 25CDissipation Rating Table Derating Factor Reference Characteristics Power ConsumptionRecommended Operating Conditions Function MIN TYP² MAX Unit Terminal ImpedanceRXIP, RXIN, RXQP, and Rxqn Inputs Avdd = 3 V, 4.5 V, 5 Parameter Test Conditions MIN TYP MAX Unit Auxiliary D/A Converters Transmit I and Q Channel OutputsParameter MIN TYP MAX Unit Auxiliary D/A Converters Slope Lcdcontr RSSI/Battery A/D ConverterAuxiliary D/A Converters Slope AGC, AFC, Pwrcont Nominal LSB Nominal Output Voltage Transmit TX Channel Frequency Response Digital Mode Transmit TX Channel Frequency Response Analog Mode Page Mclkout Mclkout Timing Requirements see ±1 and NoteVOH VOL Mcrw Parameter Alternate MIN MAX UnitMcds MCA4±MCA0 MCD7±MCD0 Mccsh Mccsl Parameter Alternate MIN MAX Unit Symbol MCA4±MCA0 MCA4±MCA0 MCD7±MCD0 Twdho Motorola 16-Bit Read Cycle, MTS 10 = MCA0±MCA4 MCD0±MCD7 Mccsh Mccsl MCA0±MCA4 Mcrw MCA0±MCA4 MCD0±MCD7 Mccsh Mccsl 10% ThR / W ThWA Dsprw DspcslDspstrbl Dspa Dspd ±11. TCM4300 to DSP Interface Write Cycle ±12 Mode Fmvox Iqrxen Fmrxen ±1. TCM4300 Receive Channel Control SignalsControl Signal Analog Mode Digital Mode Data Transfer ±2. RXIP, RXIN, RXQP, and Rxqn Inputs Avdd = 3 V, 4.5 V, 5 Transmit Section Modulation error percentage +100 s % ±5. Transmit TX I and Q Channel Outputs ±6. Transmit TX Channel Frequency Response Digital Mode Transmit Burst Operation Digital Mode±7. Transmit TX Channel Frequency Response Analog Mode ±1. Power Ramp-Up/Ramp-Down TIming Diagram Transmit I And Q Output Level Wide-Band Data Demodulator ±9. Bits in Control Register WBDCtrl ±8. Typical Bit-Error-Rate Performance Wbdbw =Wide-band Data Interrupts Parameter Test Conditions MIN MAX Unit Mean CNR Wide-band Data Demodulator General Information WBD ±10. Auxiliary D/A Converters Auxiliary DACs, LCD Contrast Converter±11. Auxiliary D /A Converters Slope AGC, AFC, Pwrcont Timing And Clock Generation RSSI, Battery Monitor±13. RSSI/Battery A/D Converter ±12. Auxiliary D /A Converters Slope Lcdcontr Microcontroller Clock Clock GenerationSpeech-Codec Clock Generation Sample Interrupt Sint Phase-Adjustment Strategy Mclkin RCOMclken Frequency Synthesizer Interface MSB/LSB First Clkpol Numclks LowvalHighval Syndta ±14. Synthesizer Control Fields Name Description Name Suggested External Application Reset Power Control Port15. External Power Control Signals Synclk Syndta SYNLE1 SYNLE0 Synrdy OUT1 Iqrxen Txen ModeWBD Wbdon Fmrxen Scen Fifo a Fifo B Microcontroller-DSP CommunicationsDint Cint DSP Microcontroller Register Map ±16. Microcontroller Register Map ±17. Microcontroller Register Definitions Wide-Band Data/Control RegisterAddr Name Category Microcontroller Status and Control Registers BIT Name Function Reset Value±18. WBDCtrl Register LDC D/A LCD Contrast±19. MStatCtrl Register Bits Lcden ±20. DSP Register Map DSP Register Map±21. DSP Register Definitions Dspcsl TCM4300 Dsprw Dspstrbl Sint Cint Bdint Wide-Band Data RegistersBase Station Offset Register DSP Strb INT DSP Status and Control Registers ±22. DStatCtrl Register Bits Internal Reset State ResetPower-On Reset ±23. Power-On Reset Register Initialization ±25. Microcontroller Interface Connections for Intel Mode Intel Microcontroller Mode Of Operation±24. Microcontroller Interface Configuration Microcontroller Interface Mcrw Mcds Mitsubishi Microcontroller Mode of OperationMotorola Microcontroller Mode of Operation IRQ NMI Dint CS3 ±32 Mechanical Data PZ S-PQFP-G100 Important Notice