Texas Instruments TCM4300 - page 13

1–5

1.4 Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME NO.

I/O

DESCRIPTION

DSPRW 69 I DSP read/write. A high on DSPRW enables a read operation and a low enables

a write operation to the DSP.

DSPSTRBL 68 I DSP strobe low. The DSPSTRL (active low) is used in conjunction with DSPCSL

to enable read/write operations to the DSP.

DVDD 35, 45, 63,

75, 90 —Digital power supply. All supply terminals must be connected together.

DVSS 34, 46, 65,

76, 91 —Digital ground. All supply terminals must be connected together.

DWBDINT 78 O DSP wide-band data interrupt (active low). The DWBDINT output goes low to

indicate that the wide-band data (WBD) demodulation circuits have traffic on

them.

FM 4 I Frequency modulation. FM terminal is connected to the output of the FM

discriminator.

FMRXEN 95 O FM receive path enable. A high output from FMRXEN can be used to enable the

power for the receiver FM path.

IQRXEN 96 O In-phase and quadrature receive path enable. A high output on IQRXEN can be

used to enable the power for receiver I/Q path.

LCDCONTR 33 O Liquid-crystal display (LCD) contrast. This LCDCONTR control DAC can be

used to control the amount of drive to the liquid crystal display.

MCLKOUT 67 O Master clock out. MCLKOUT is a buffered version of MCLKIN.

MCA0 40 IMicrocontroller 5-bit parallel address bus. MCA0 through MCA4 provide a 5-bit

b t dd th i t ll MCA4 i th MSB dMCA0 i th LSB

MCA1 41

pgp

bus to address the microcontroller. MCA4 is the MSB, and MCA0 is the LSB.

MCA2 42

MCA3 43

MCA4 44

MCCLK 62 O Microcontroller clock. MCCLK provides an adjustable frequency with 1.215 MHz

at powerup.

MCCSH 39 I Microcontroller interface chip-select. A high at MCCSH in conjunction with a low

at MCCSL allows the microcontroller to read from or write to the TCM4300.

MCCSL 38 I Microcontroller interface chip-select. A low at MCCSL in conjunction with a high

at the MCCSH allows the microcontroller to read from or write to the TCM4300.

MCD0 51 I/O/Z Microcontroller 8-bit parallel data bus. MCD0 through MCD7 provides an 8-bit

ll ld t b t d/ i d t t /f th i t ll MCD7 i th

MCD1 52

pgp

parallel data bus to send/receive data to/from the microcontroller. MCD7 is the

MSB and MCD0 is the LSB

MCD2 53

MSB

, an

d

MCD0

i

s

th

e

LSB

.

MCD3 54

MCD4 55

MCD5 56

MCD6 57

MCD7 58

†Z = high impedance

Contents

Main Page Page Page Contents Section Title Page Page List of Illustrations Figure Title Page List of Tables Table Title Page 1 Introduction 1.1 Features 12 1.2 TCM4300 Functional Block Diagram 1.3 Pin Assignments 1.4 Terminal Functions Page Page Page 2 Electrical Specifications 2.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless otherwise noted) 2.2 Dissipation Rating Table 2.3 Recommended Operating Conditions 2.4 Electrical Characteristics Over Full Range Of Operating Conditions (Unless Otherwise Noted) 2.4.1 Power Consumption 2.4.2 Reference Characteristics 2.4.3 Terminal Impedance 2.4.4 RXIP, RXIN, RXQP, and RXQN Inputs (AVDD = 3 V, 4.5 V, 5 V) 2.4.5 Transmit I and Q Channel Outputs 2.4.6 Auxiliary D/A Converters 2.4.7 Auxiliary D/A Converters Slope (AGC, AFC, PWRCONT) 2.4.8 Auxiliary D/A Converters Slope (LCDCONTR) 2.4.9 RSSI/Battery A/D Converter 2.5 Operating Characteristics Over Full Range of Operating Conditions (Unless Otherwise Noted) 2.5.1 Receive (RX) Channel Frequency Response (RXI, RXQ Input in Digital Mode) 2.5.2 Receive (RX) Channel Frequency Response (FM Input in Analog Mode) 2.5.3 Transmit (TX) Channel Frequency Response (Digital Mode) 2.5.4 Transmit (TX) Channel Frequency Response (Analog Mode) Page 3 Parameter Measurement Information 3.1 MCLKOUT Timing Requirements (see Figure 31 and Note 1) Page Page Page Page Page Page Page Page 3.10 Switching Characteristics, TCM4300 to DSP Interface (Read Cycle) (see Figure 310) Figure 310. TCM4300 to DSP Interface (Read Cycle) 3.11 Switching Characteristics, TCM4300 to DSP Interface (Write Cycle) (see Figure 311) Figure 311. TCM4300 to DSP Interface (Write Cycle) Page 4 Principles of Operation 4.1 Data Transfer 4.2 Receive Section Table 42. RXIP, RXIN, RXQP, and RXQN Inputs (AVDD = 3 V, 4.5 V, 5 V) 4.3 Transmit Section Modulation error percentage 100 |e| |s| % 4.4 Transmit Burst Operation (Digital Mode) Page 4.5 Transmit I And Q Output Level 4.6 Wide-Band Data Demodulator 4.7 Wide-band Data Interrupts 4.8 Wide-band Data Demodulator General Information 4.9 Auxiliary DACs, LCD Contrast Converter 4.9 Auxiliary DACs, LCD Contrast Converter (continued) 4.10 RSSI, Battery Monitor 4.11 Timing And Clock Generation 4.11.1 Clock Generation 4.11.2 Speech-Codec Clock Generation MCLKIN 4.11.3 Microcontroller Clock 4.11.4 Sample Interrupt SINT 4.11.5 Phase-Adjustment Strategy Figure 45. Timing and Clock Generation for 38.88-MHz Clock 4.12 Frequency Synthesizer Interface Figure 46. Synthesizer Interface Circuit Block Diagram Page 4.13 Power Control Port Page 4.14 Microcontroller-DSP Communications 421 4.15 Microcontroller Register Map Table 417. Microcontroller Register Definitions 4.16 Wide-Band Data/Control Register 4.17 Microcontroller Status and Control Registers Table 419. MStatCtrl Register Bits 4.18 LCD Contrast 4.19 DSP Register Map Table 421. DSP Register Definitions Figure 411. DSP Interface 4.20 Wide-Band Data Registers Bit 9 of the wide-band data register is the most recently received bit as shown below. 4 4.21 Base Station Offset Register The delay in the TCM4300 TX channels is increased by the amount: BST OFFSET dTSINT 4.22 DSP Status and Control Registers 4.23 Reset 4.23.1 Power-On Reset 4.23.2 Internal Reset State 4.24 Microcontroller Interface 4.24.1 Intel Microcontroller Mode Of Operation 4.24.2 Mitsubishi Microcontroller Mode of Operation 4.24.3 Motorola Microcontroller Mode of Operation Table 428. Microcontroller Interface Connections for Motorola Mode (16 bits) Page 5 Mechanical Data 5.1