Texas Instruments TCM4300 manual Rco, Mclkin, Mclken

		⎟17, 18, 19, 20		2.048-MHz Codec Master Clock CMCLK
			= 0	⎟256
		Adjust	Bits 0 ± 5	RCO	8-kHz Codec Sample Clock CSCLK
		Counter B
From DSP	10
			Phase-Adjusted
		Adjust	9.72-MHz Clock
		Counter A
38.88 MHz					Analog/Digital
			⎟243/	40.0/48.6-kHz A/ D Sample Clock (SINT)
MCLKIN		⎟3, 4, 5
			⎟200
		Analog/Digital
		Mode (MODE bit)
					Frequency Synth. Clock 303.75 kHz
			Clock		WBD Demod. 6.48 MHz
			Divider		ADC Clocks
From	5		Chain		DAC Clocks
Micro-
controller		⎟N			Microcontroller Clock MCCLK
		N = (2, 3, . . . 32)
			Sync.		External Clock Output MCLKOUT
			Enable
		MCLKEN	Logic

Figure 4±5. Timing and Clock Generation for 38.88-MHz Clock

4±14