Auxiliary D/A Converters Slope Lcdcontr | Texas Instruments TCM4300

2.4.7Auxiliary D/A Converters Slope (AGC, AFC, PWRCONT)

			NOMINAL LSB	NOMINAL OUTPUT VOLTAGE	NOMINAL OUTPUT VOLTAGE
	AUXFS[1:0]		NOMINAL LSB	FOR DIGITAL CODE = 128	FOR DIGITAL CODE = 256²
	AUXFS[1:0]	SLOPE	VALUE	FOR DIGITAL CODE = 128	FOR DIGITAL CODE = 256²
	SETTING	SLOPE	VALUE	(MIDRANGE)	(MAX VALUE)
	SETTING		(V)	(MIDRANGE)	(MAX VALUE)
			(V)	(V)	(V)
				(V)	(V)

	00	2.5/256	0.0098	1.25	2.5

	01	Do not use	Do not use	Do not use	Do not use

	10	4/256	0.0156	2	4

	11	4.5/256	0.0176	2.25	4.5

² The maximum input code is 255. The value shown for 256 is extrapolated.

2.4.8Auxiliary D/A Converters Slope (LCDCONTR)

			NOMINAL LSB	NOMINAL OUTPUT VOLT-	NOMINAL OUTPUT VOLTAGE
	AUXFS[1:0]		NOMINAL LSB	AGE FOR DIGITAL CODE = 8	FOR DIGITAL CODE = 16§
	AUXFS[1:0]	SLOPE	VALUE	AGE FOR DIGITAL CODE = 8	FOR DIGITAL CODE = 16§
	SETTING	SLOPE	VALUE	(MIDRANGE)	(MAX VALUE)
	SETTING		(V)	(MIDRANGE)	(MAX VALUE)
			(V)	(V)	(V)
				(V)	(V)

	00	2.5/16	0.1563	1.25	2.5

	01	Do not use	Do not use	Do not use	Do not use

	10	4/16	0.2500	2	4

	11	4.5/16	0.2813	2.25	4.5

³The maximum input code is 15. The value shown for 16 is extrapolated.

2.4.9RSSI/Battery A/D Converter

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT

Input range	AVDD = 3 V, 4.5 V, 5 V	0.2		2	V
Resolution			8		bits

Conversion time	AVDD = 3 V, 4.5 V, 5 V		20		μs
Gain + offset error (full scale)			± 3%	± 4%

Differential nonlinearity			± 0.75	± 1	LSB

Integral nonlinearity			± 0.75	± 1	LSB

Input resistance		1	2		MΩ

2±5

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Texas Instruments TCM4300 manual Auxiliary D/A Converters Slope AGC, AFC, Pwrcont, Auxiliary D/A Converters Slope Lcdcontr

Contents

Data Manual SLWS010F TCM4300 Data Manual Important Notice Contents Mechanical Data ±1 List of Illustrations List of Tables Features Introduction TCM4300 Functional Block Diagram Pin Assignments PZ Package TOP ViewVSS Fmrxen Terminal Functions Terminal Description Name Dsprw DspstrblDvdd Dvss Mcds MTS1Mclkin Mcrw Scen SintSynclk Syndta Power Rating Above TA = 25C Dissipation Rating TablePackage Derating Factor Recommended Operating Conditions Power ConsumptionReference Characteristics Terminal Impedance RXIP, RXIN, RXQP, and Rxqn Inputs Avdd = 3 V, 4.5 V, 5Function MIN TYP² MAX Unit Parameter Test Conditions MIN TYP MAX Unit Parameter MIN TYP MAX Unit Transmit I and Q Channel OutputsAuxiliary D/A Converters RSSI/Battery A/D Converter Auxiliary D/A Converters Slope AGC, AFC, PwrcontAuxiliary D/A Converters Slope Lcdcontr Nominal LSB Nominal Output Voltage Transmit TX Channel Frequency Response Digital Mode Transmit TX Channel Frequency Response Analog Mode Page VOH VOL Mclkout Timing Requirements see ±1 and NoteMclkout Parameter Alternate MIN MAX Unit McdsMcrw MCA4±MCA0 MCD7±MCD0 Mccsh Mccsl Parameter Alternate MIN MAX Unit Symbol MCA4±MCA0 MCA4±MCA0 MCD7±MCD0 Twdho Motorola 16-Bit Read Cycle, MTS 10 = MCA0±MCA4 MCD0±MCD7 Mccsh Mccsl MCA0±MCA4 Mcrw MCA0±MCA4 MCD0±MCD7 Mccsh Mccsl 10% ThR / W ThWA Dspcsl DspstrblDsprw Dspa Dspd ±11. TCM4300 to DSP Interface Write Cycle ±12 ±1. TCM4300 Receive Channel Control Signals Control Signal Analog Mode Digital ModeMode Fmvox Iqrxen Fmrxen Data Transfer ±2. RXIP, RXIN, RXQP, and Rxqn Inputs Avdd = 3 V, 4.5 V, 5 Transmit Section Modulation error percentage +100 s % ±5. Transmit TX I and Q Channel Outputs ±7. Transmit TX Channel Frequency Response Analog Mode Transmit Burst Operation Digital Mode±6. Transmit TX Channel Frequency Response Digital Mode ±1. Power Ramp-Up/Ramp-Down TIming Diagram Transmit I And Q Output Level Wide-Band Data Demodulator ±8. Typical Bit-Error-Rate Performance Wbdbw = Wide-band Data Interrupts±9. Bits in Control Register WBDCtrl Parameter Test Conditions MIN MAX Unit Mean CNR Wide-band Data Demodulator General Information WBD ±11. Auxiliary D /A Converters Slope AGC, AFC, Pwrcont Auxiliary DACs, LCD Contrast Converter±10. Auxiliary D/A Converters RSSI, Battery Monitor ±13. RSSI/Battery A/D ConverterTiming And Clock Generation ±12. Auxiliary D /A Converters Slope Lcdcontr Clock Generation Speech-Codec Clock GenerationMicrocontroller Clock Sample Interrupt Sint Phase-Adjustment Strategy Mclken RCOMclkin Frequency Synthesizer Interface Clkpol Numclks Lowval HighvalMSB/LSB First Syndta ±14. Synthesizer Control Fields Name Description Power Control Port 15. External Power Control SignalsName Suggested External Application Reset Synclk Syndta SYNLE1 SYNLE0 Synrdy Iqrxen Txen Mode WBD WbdonOUT1 Fmrxen Scen Microcontroller-DSP Communications DintFifo a Fifo B Cint DSP Microcontroller Register Map ±16. Microcontroller Register Map Addr Name Category Wide-Band Data/Control Register±17. Microcontroller Register Definitions ±18. WBDCtrl Register BIT Name Function Reset ValueMicrocontroller Status and Control Registers LCD Contrast ±19. MStatCtrl Register BitsLDC D/A Lcden ±21. DSP Register Definitions DSP Register Map±20. DSP Register Map Wide-Band Data Registers Base Station Offset RegisterDspcsl TCM4300 Dsprw Dspstrbl Sint Cint Bdint DSP Strb INT DSP Status and Control Registers ±22. DStatCtrl Register Bits Reset Power-On ResetInternal Reset State ±23. Power-On Reset Register Initialization Intel Microcontroller Mode Of Operation ±24. Microcontroller Interface Configuration±25. Microcontroller Interface Connections for Intel Mode Microcontroller Interface Mitsubishi Microcontroller Mode of Operation Motorola Microcontroller Mode of OperationMcrw Mcds IRQ NMI Dint CS3 ±32 Mechanical Data PZ S-PQFP-G100 Important Notice