Texas Instruments TCM4300 manual MCA4±MCA0 MCD7±MCD0

3.4TCM4300 to Microcontroller Interface Timing Requirements (Intel Read Cycle) (see Figure 3±4 and Note 3)

PARAMETER

ALTERNATE

MIN MAX

UNIT

SYMBOL

tsu(RA)

Setup time, read address MCA stable before falling edge of

TRA(SU)

0

ns

strobe MCDS

th(RA)

Hold time, read address MCA stable after rising edge of

TRA(HO)

10

ns

strobe MCDS

ten(RD)

Enable time, read data on falling edge of strobe MCDS to

TRD(EN)

10

ns

TCM4300 driving data bus MCD

tv(RD)

Valid time, read data on falling edge of strobe MCDS to

TRD(DV)

50

ns

valid data MCD

tinv

Data MCD invalid after rising edge of strobe MCDS

TRD(INV)

10

ns

tdis(RD)

Disable time, read data. TCM4300 releases MCD data bus

TRD(DIS)

28

ns

after rising edge of strobe MCDS

tsu(CS)

Setup time, chip select MCCSH and MCCSL stable before

TCS(SU)

0

ns

falling edge of strobe MCDS

th(CS)

Hold time, chip select MCCSH and MCCSL stable before

TCS(HO)

0

ns

rising edge of strobe MCDS

NOTE 3: Timings are based upon Intel 80C186 (16 MHz).

90%

90%

MCDS

10%

10%

(see Note A)

MCRW

tsu(RA)

th(RA)

MCA4±MCA0

MCD7±MCD0

ten(RD)

tv(RD)

tinv

tdis(RD)

MCCSH

tsu(CS)

MCCSL

90%	90%
	th(CS)
10%	10%

NOTE A: Chip selection is defined as both MCCS and MCDS active.

Figure 3±4. Microcontroller Interface Timing Requirements

(Intel Configuration Read Cycle, MTS [1:0] = 00)

3±4