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2.11 Packet Receive Operation
2.11.1Receive DMA Host Configuration
To configure the receive DMA for operation the host must:
•Initialize the receive addresses.
•Initialize the receive channel n DMA head descriptor pointer registers (RXnHDP) to 0.
•Write the MAC address hash n registers (MACHASH1 and MACHASH2), if hash matching multicast addressing is desired.
•If flow control is to be enabled, initialize:
–the receive channel n free buffer count registers (RXnFREEBUFFER)
–the receive channel n flow control threshold register (RXnFLOWTHRESH)
–the receive filter low priority frame threshold register (RXFILTERLOWTHRESH)
•Enable the desired receive interrupts using the receive interrupt mask set register (RXINTMASKSET) and the receive interrupt mask clear register (RXINTMASKCLEAR).
•Set the appropriate configuration bits in the MAC control register (MACCONTROL).
•Write the receive buffer offset register (RXBUFFEROFFSET) value (typically zero).
•Setup the receive channel(s) buffer descriptors and initialize RXnHDP.
•Enable the receive DMA controller by setting the RXEN bit in the receive control register (RXCONTROL).
•Configure and enable the receive operation, as desired, in the receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE) and by using the receive unicast set register (RXUNICASTSET) and the receive unicast clear register (RXUNICASTCLEAR).
2.11.2Receive Channel Enabling
Each of the eight receive channels has an enable bit (RXCHnEN) in the receive unicast enable set register (RXUNICASTSET) that is controlled using RXUNICASTSET and the receive unicast clear register (RXUNICASTCLEAR). The RXCHnEN bits determine whether the given channel is enabled (set to 1) to receive frames with a matching unicast or multicast destination address.
The RXBROADEN bit in the receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE) determines if broadcast frames are enabled or filtered. If broadcast frames are enabled, then they are copied to only a single channel selected by the RXBROADCH field in
RXMBPENABLE.
The RXMULTEN bit in RXMBPENABLE determines if hash matching multicast frames are enabled or filtered. Incoming multicast addresses (group addresses) are hashed into an index in the hash table. If the indexed bit is set, the frame hash will match and it will be transferred to the channel selected by the RXMULTCH field in RXMBPENABLE when multicast frames are enabled. The multicast hash bits are set in the MAC address hash n registers (MACHASH1 and MACHASH2).
The RXPROMCH bits in RXMBPENABLE select the promiscuous channel to receive frames selected by the RXCMFEN, RXCSFEN, RXCEFEN, and RXCAFEN bits. These four bits allow reception of MAC control frames, short frames, error frames, and all frames (promiscuous), respectively.
The address RAM can be configured to set multiple unicast and/or multicast addresses to a given channel (if the match bit is set in the RAM). Multicast addresses in the RAM are enabled by RXUNICASTSET and not by the RXMULTEN bit in RXMBPENABLE, the RXMULTEN bit enables the hash multicast match only. The address RAM takes precedence over the hash match.
If a multicast packet is received that hash matches (multicast packets enabled), but is filtered in the RAM, then the packet is filtered. If a multicast packet does not hash match, regardless of whether or not hash matching is enabled, but matches an enabled multicast address in the RAM, then the packet will be transferred to the associated channel.
44 Ethernet Media Access Controller (EMAC)/Management Data Input/Output SPRUFI5B
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