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3.2EMAC Control Module Software Reset Register (CMSOFTRESET)
The software reset register (CMSOFTRESET) is shown in Figure 13 and described in Table 9.
Figure 13. EMAC Control Module Software Reset Register (CMSOFTRESET)
31 |
| 16 |
Reserved |
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15 | 1 | 0 |
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Reserved |
| SOFTRESET |
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LEGEND: R/W = Read/Write; R = Read only;
Table 9. EMAC Control Module Software Reset Register (CMSOFTRESET) Field Descriptions
Bit | Field | Value | Description |
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Reserved | 0 | Reserved | |
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0 | SOFTRESET |
| Software reset. |
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| 0 | No effect. |
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| 1 | Causes the EMAC control module logic to be reset. Software reset occurs on the clock following the |
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| register bit write. |
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3.3EMAC Control Module Emulation Control Register (CMEMCONTROL)
The emulation control register (CMEMCONTROL) is shown in Figure 14 and described in Table 10.
Figure 14. EMAC Control Module Emulation Control Register (CMEMCONTROL)
31 |
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| 16 |
Reserved |
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15 | 2 | 1 | 0 |
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Reserved |
| SOFT | FREE |
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LEGEND: R/W = Read/Write; R = Read only;
Table 10. EMAC Control Module Emulation Control Register (CMEMCONTROL)
Field Descriptions
Bit | Field | Value | Description |
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Reserved | 0 | Reserved | |
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1 | SOFT |
| Emulation soft bit. This bit is used in conjunction with FREE bit to determine the emulation suspend |
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| mode. This bit has no effect if FREE = 1. |
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| 0 | Soft mode is disabled. EMAC control module stops immediately during emulation halt. |
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| 1 | Soft mode is enabled. During emulation halt, EMAC control module stops after completion of current |
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| operation. |
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0 | FREE |
| Emulation free bit. This bit is used in conjunction with SOFT bit to determine the emulation suspend |
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| mode. |
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| 0 | |
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| control module. |
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| 1 | |
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SPRUFI5B
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