Texas Instruments TMS320DM36X instruction

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Ethernet Media Access Controller (EMAC) Registers

5.8Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)

The transmit interrupt status (masked) register (TXINTSTATMASKED) is shown in Figure 47 and described in Table 45.

	Figure 47. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)
31									16

			Reserved

				R-0
15									8

			Reserved

				R-0
7	6	5	4	3		2	1		0

TX7PEND	TX6PEND	TX5PEND	TX4PEND		TX3PEND	TX2PEND	TX1PEND		TX0PEND

R-0	R-0	R-0	R-0		R-0	R-0	R-0		R-0

LEGEND: R = Read only; -n= value after reset

Table 45. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions

Bit	Field	Value	Description

31-8	Reserved	0	Reserved

7	TX7PEND	0-1	TX7PEND masked interrupt read

6	TX6PEND	0-1	TX6PEND masked interrupt read

5	TX5PEND	0-1	TX5PEND masked interrupt read

4	TX4PEND	0-1	TX4PEND masked interrupt read

3	TX3PEND	0-1	TX3PEND masked interrupt read

2	TX2PEND	0-1	TX2PEND masked interrupt read

1	TX1PEND	0-1	TX1PEND masked interrupt read

0	TX0PEND	0-1	TX0PEND masked interrupt read

SPRUFI5B –March 2009 –Revised December 2010 Ethernet Media Access Controller (EMAC)/Management Data Input/Output 91

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Texas Instruments TMS320DM36X manual Transmit Interrupt Status Masked Register Txintstatmasked

Contents

Users Guide Submit Documentation Feedback Mdio Registers Mdio Version Register Version Mdio Control Register Control Appendix B Appendix a List of Figures Transmit Interrupt Mask Set Register Txintmaskset List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Related Documentation From Texas Instruments Related Documentation From Texas Instruments Purpose of the Peripheral Features Emac and Mdio Block Diagram Functional Block Diagram Clock Control Industry Standards Compliance StatementMII Clocking Memory Map Signal DescriptionsMedia Independent Interface MII Connections Signal Type Description Emac and Mdio Signals for MII InterfacePin Multiplexing Field Bytes Description Ethernet Protocol OverviewEthernet Frame Format Ethernet Frame Description Word Ethernet’s Multiple Access ProtocolProgramming Interface Packet Buffer Descriptors Field Field Description Basic Descriptor Description Transmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Example 1. Transmit Buffer Descriptor in C Structure Format Transmit Buffer Descriptor Format Buffer Length Next Descriptor PointerBuffer Pointer Buffer Offset Teardown Complete Tdowncmplt Flag End of Packet EOP FlagOwnership Owner Flag End of Queue EOQ Flag Receive Buffer Descriptor Format Receive Buffer Descriptor Format Example 2. Receive Buffer Descriptor in C Structure Format Buffer Length Jabber Flag Code Error Codeerror FlagAlignment Error Alignerror Flag CRC Error Crcerror Flag CPU Emac Control ModuleInternal Memory Bus Arbiter Transmit Pulse Interrupt Interrupt ControlReceive Pulse Interrupt Miscellaneous Pulse Interrupt Receive Threshold Pulse InterruptInterrupt Pacing Global PHY Detection and Link State Monitoring Mdio ModuleMdio Module Components Mdio Clock Generator Active PHY Monitoring PHY Register User AccessMdio Module Operational Overview Writing Data To a PHY Register Initializing the Mdio ModuleReading Data From a PHY Register Example 3. Mdio Register Access Macros Example of Mdio Register Access Code Receive Fifo Emac ModuleEmac Module Components Receive DMA Engine Transmit DMA Engine Clock and Reset LogicMAC Receiver Receive Address Emac Module Operational Overview Receive Inter-Frame Interval Media Independent Interface MIIData Reception Receive Control Ieee 802.3x-Based Receive Buffer Flow Control Collision-Based Receive Buffer Flow Control Interpacket-Gap IPG Enforcement Transmit ControlCRC Insertion Adaptive Performance Optimization APO Speed, Duplex, and Pause Frame Support Transmit Flow Control Packet Receive Operation Receive DMA Host ConfigurationReceive Channel Enabling Hardware Receive QOS Support Receive Address Matching Receive Channel Teardown Host Free Buffer TrackingReceive Frame Classification Receive Frame Treatment Summary Promiscuous Receive ModeReceive Frame Treatment Middle of Frame Overrun Treatment Receive OverrunMiddle of Frame Overrun Treatment Transmit Channel Teardown Transmit DMA Host ConfigurationPacket Transmit Operation Receive and Transmit Latency Software Reset Considerations Reset ConsiderationsTransfer Node Priority Emac Control Module Initialization Hardware Reset ConsiderationsInitialization Enabling the EMAC/MDIO Peripheral Example 4. Emac Control Module Initialization Code Example 5. Mdio Module Initialization Code Mdio Module Initialization Emac Module Initialization Transmit Packet Completion Interrupts Interrupt SupportEmac Module Interrupt Events and Requests Receive Threshold Interrupts Receive Packet Completion Interrupts Statistics Interrupt Host Error Interrupt Proper Interrupt Processing User Access Completion InterruptMdio Module Interrupt Events and Requests Link Change Interrupt Soft Free Description Power ManagementEmulation Considerations Emulation Control Bit Field Value Description Emac Control Module RegistersSlave Vbus Acronym Register Description Soft Free Emac Control Module Software Reset Register CmsoftresetSoftreset Emac Control Module Emulation Control Register Cmemcontrol Intpaceen Emac Control Module Interrupt Control Register CmintctrlIntprescale Rxpulseen Rxthreshen Txpulseen Bit Field Statpendinten Hostpendinten Linkinten UserintenStatpendinten Rxpulseinttstat Rxthreshinttstat 31-8 Reserved TXPULSEINTTSTATn Txpulseinttstat Statpendintstat Statpendintstat Hostpendintstat Linkintstat Userintstat Tximax Rximax Management Data Input/Output Mdio Registers Mdio Version Register VersionMdio Version Register Version Field Descriptions Mdio Control Register Control Field Descriptions Mdio Control Register Control PHY Link Status Register Link Field Descriptions PHY Acknowledge Status Register AlivePHY Link Status Register Link PHY Acknowledge Status Register Alive Field Descriptions 31-2 Reserved Will clear the event and writing a 0 has no effect No Mdio user command complete event USERINTMASKED0 and USERINTMASKED1 correspond to USERACCESS0 W1S-0 Mdio User Command Complete Interrupt Mask Clear Register Mdio User Command Complete Interrupt Mask Clear Register Mdio User Access Register 0 USERACCESS0 Field Descriptions Mdio User Access Register 0 USERACCESS0 Linksel Mdio User PHY Select Register 0 USERPHYSEL0Linksel Linkintenb Phyadrmon Mdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User Access Register 1 USERACCESS1 Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1 Ethernet Media Access Controller Emac Registers Offset Acronym Register Description Network Statistics Registers Transmit Control Register Txcontrol Transmit Identification and Version Register TxidverTransmit Control Register Txcontrol Field Descriptions Transmit Teardown Register Txteardown Field Descriptions Transmit Teardown Register TxteardownTxtdnch Rxmajorver Receive Identification and Version Register RxidverRxident Rxmajorver Rxminorver Receive Teardown Register Rxteardown Field Descriptions Receive Control Register RxcontrolReceive Teardown Register Rxteardown Receive Control Register Rxcontrol Field Descriptions TX7PEND Transmit Interrupt Status Unmasked Register Txintstatraw Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register Txintstatmasked TX7MASK Transmit Interrupt Mask Set Register Txintmaskset Transmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register Txintmaskclear Statpend MAC Input Vector Register MacinvectorMAC End Of Interrupt Vector Register Maceoivector MAC Input Vector Register Macinvector Field Descriptions RX7PEND Receive Interrupt Status Unmasked Register Rxintstatraw Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register Rxintstatmasked RX7MASK Receive Interrupt Mask Set Register Rxintmaskset Receive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register Rxintmaskclear MAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Status Unmasked Register MacintstatrawHostpend Statpend Hostmask MAC Interrupt Mask Set Register MacintmasksetMAC Interrupt Mask Clear Register Macintmaskclear Hostmask Statmask Rxpromch Rxpasscrc Rxqosen RxnochainRxcmfen Rxcsfen Rxcefen Rxcafen Frames containing errors are filtered Receive multicast channel select RXCH7EN Receive Unicast Enable Set Register Rxunicastset Receive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register Rxunicastclear Receive Buffer Offset Register Rxbufferoffset Receive Maximum Length Register RxmaxlenReceive Maximum Length Register Rxmaxlen Field Descriptions Rxfilterthresh Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol Field Descriptions MAC Control Register Maccontrol Fullduplex TxflowenRxbufferflowen Loopback MAC Status Register Macstatus Field Descriptions MAC Status Register Macstatus Rxqosact Fifo Control Register Fifocontrol Field Descriptions Emulation Control Register EmcontrolFifo Control Register Fifocontrol Emulation Control Register Emcontrol Field Descriptions Soft Reset Register Softreset Field Descriptions MAC Configuration Register MacconfigSoft Reset Register Softreset MAC Configuration Register Macconfig Field Descriptions MAC Source Address High Bytes Register Macsrcaddrhi MAC Source Address Low Bytes Register Macsrcaddrlo MAC Hash Address Register 2 MACHASH2 Field Descriptions MAC Hash Address Register 1 MACHASH1MAC Hash Address Register 2 MACHASH2 MAC Hash Address Register 1 MACHASH1 Field Descriptions Transmit Pacing Algorithm Test Register Tpacetest Back Off Test Register BofftestBack Off Test Register Bofftest Field Descriptions Transmit Pause Timer Register Txpause Field Descriptions Receive Pause Timer Register RxpauseTransmit Pause Timer Register Txpause Receive Pause Timer Register Rxpause Field Descriptions Valid MAC Address Low Bytes Register MacaddrloMAC Address Low Bytes Register Macaddrlo Field Descriptions Valid Matchfilt Channel MACADDR0 MACADDR1 MACADDR2 MACADDR3 MACADDR4 MACADDR5 MAC Address High Bytes Register MacaddrhiMAC Index Register Macindex MAC Index Register Macindex Field Descriptions TXnHDP Receive Channel 0-7 Completion Pointer Register RXnCP Transmit Channel 0-7 Completion Pointer Register TXnCP Multicast Receive Frames Register Rxmcastframes Network Statistics RegistersGood Receive Frames Register Rxgoodframes Broadcast Receive Frames Register Rxbcastframes Receive Oversized Frames Register Rxoversized Receive CRC Errors Register RxcrcerrorsReceive Alignment/Code Errors Register Rxaligncodeerrors Pause Receive Frames Register Rxpauseframes Filtered Receive Frames Register Rxfiltered Receive Jabber Frames Register RxjabberReceive Undersized Frames Register Rxundersized Receive Frame Fragments Register Rxfragments Broadcast Transmit Frames Register Txbcastframes Receive QOS Filtered Frames Register RxqosfilteredReceive Octet Frames Register Rxoctets Good Transmit Frames Register Txgoodframes Transmit Single Collision Frames Register Txsinglecoll Pause Transmit Frames Register TxpauseframesDeferred Transmit Frames Register Txdeferred Transmit Collision Frames Register Txcollision Transmit Octet Frames Register Txoctets Transmit Underrun Error Register TxunderrunTransmit Carrier Sense Errors Register Txcarriersense Transmit Late Collision Frames Register Txlatecoll Submit Documentation Feedback Receive DMA Overruns Register Rxdmaoverruns Network Octet Frames Register Netoctets Appendix a Glossary Term Definition Physical Layer Definitions Reference Additions/Modifications/Deletions Document Revision History DSP Products ApplicationsRfid