W1S-0 | Texas Instruments TMS320DM36X specification

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MDIO Registers

4.9MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)

The MDIO user command complete interrupt mask set register (USERINTMASKSET) is shown in Figure 34 and described in Table 31.

Figure 34. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)

31			16
	Reserved

	R-0
15	2	1	0

Reserved		USERINTMASKSET

R-0			R/W1S-0

LEGEND: R = Read only; R/W = Read/Write; W1S = Write 1 to set, write of 0 has no effect; -n= value after reset

Table 31. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)

Field Descriptions

Bit	Field	Value	Description

31-2	Reserved	0	Reserved

1-0	USERINTMASKSET	0-3h	MDIO user interrupt mask set for USERINTMASKED[1:0], respectively. Setting a bit to 1 will
			enable MDIO user command complete interrupts for that particular USERACCESS register.
			MDIO user interrupt for a particular USERACCESS register is disabled if the corresponding bit
			is 0. USERINTMASKSET[0] and USERINTMASKSET[1] correspond to USERACCESS0 and
			USERACCESS1, respectively. Writing a 0 to this register has no effect.
		0	MDIO user command complete interrupts for the MDIO user access register n
			(USERACCESSn) are disabled.
		1	MDIO user command complete interrupts for the MDIO user access register n
			(USERACCESSn) are enabled.

SPRUFI5B –March 2009 –Revised December 2010 Ethernet Media Access Controller (EMAC)/Management Data Input/Output 77

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Texas Instruments TMS320DM36X manual W1S-0

Contents

Users Guide Submit Documentation Feedback Mdio Registers Mdio Version Register Version Mdio Control Register Control Appendix B Appendix a List of Figures Transmit Interrupt Mask Set Register Txintmaskset List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Related Documentation From Texas Instruments Related Documentation From Texas Instruments Purpose of the Peripheral Features Emac and Mdio Block Diagram Functional Block Diagram MII Clocking Industry Standards Compliance StatementClock Control Media Independent Interface MII Connections Signal DescriptionsMemory Map Pin Multiplexing Emac and Mdio Signals for MII InterfaceSignal Type Description Ethernet Frame Format Ethernet Protocol OverviewEthernet Frame Description Field Bytes Description Programming Interface Ethernet’s Multiple Access ProtocolPacket Buffer Descriptors Word Field Field Description Basic Descriptor Description Transmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Example 1. Transmit Buffer Descriptor in C Structure Format Transmit Buffer Descriptor Format Buffer Pointer Next Descriptor PointerBuffer Offset Buffer Length Ownership Owner Flag End of Packet EOP FlagEnd of Queue EOQ Flag Teardown Complete Tdowncmplt Flag Receive Buffer Descriptor Format Receive Buffer Descriptor Format Example 2. Receive Buffer Descriptor in C Structure Format Buffer Length Alignment Error Alignerror Flag Code Error Codeerror FlagCRC Error Crcerror Flag Jabber Flag Internal Memory Emac Control ModuleBus Arbiter CPU Receive Pulse Interrupt Interrupt ControlTransmit Pulse Interrupt Interrupt Pacing Receive Threshold Pulse InterruptMiscellaneous Pulse Interrupt Mdio Module Components Mdio ModuleMdio Clock Generator Global PHY Detection and Link State Monitoring Mdio Module Operational Overview PHY Register User AccessActive PHY Monitoring Reading Data From a PHY Register Initializing the Mdio ModuleWriting Data To a PHY Register Example 3. Mdio Register Access Macros Example of Mdio Register Access Code Emac Module Components Emac ModuleReceive DMA Engine Receive Fifo MAC Receiver Clock and Reset LogicReceive Address Transmit DMA Engine Emac Module Operational Overview Data Reception Media Independent Interface MIIReceive Control Receive Inter-Frame Interval Ieee 802.3x-Based Receive Buffer Flow Control Collision-Based Receive Buffer Flow Control CRC Insertion Transmit ControlAdaptive Performance Optimization APO Interpacket-Gap IPG Enforcement Speed, Duplex, and Pause Frame Support Transmit Flow Control Receive Channel Enabling Receive DMA Host ConfigurationPacket Receive Operation Hardware Receive QOS Support Receive Address Matching Receive Frame Classification Host Free Buffer TrackingReceive Channel Teardown Receive Frame Treatment Promiscuous Receive ModeReceive Frame Treatment Summary Middle of Frame Overrun Treatment Receive OverrunMiddle of Frame Overrun Treatment Packet Transmit Operation Transmit DMA Host ConfigurationReceive and Transmit Latency Transmit Channel Teardown Transfer Node Priority Reset ConsiderationsSoftware Reset Considerations Initialization Hardware Reset ConsiderationsEnabling the EMAC/MDIO Peripheral Emac Control Module Initialization Example 4. Emac Control Module Initialization Code Example 5. Mdio Module Initialization Code Mdio Module Initialization Emac Module Initialization Emac Module Interrupt Events and Requests Interrupt SupportReceive Threshold Interrupts Transmit Packet Completion Interrupts Receive Packet Completion Interrupts Statistics Interrupt Host Error Interrupt Mdio Module Interrupt Events and Requests User Access Completion InterruptLink Change Interrupt Proper Interrupt Processing Emulation Considerations Power ManagementEmulation Control Soft Free Description Slave Vbus Emac Control Module RegistersAcronym Register Description Bit Field Value Description Softreset Emac Control Module Software Reset Register CmsoftresetEmac Control Module Emulation Control Register Cmemcontrol Soft Free Intprescale Emac Control Module Interrupt Control Register CmintctrlIntpaceen Rxpulseen Rxthreshen Txpulseen Statpendinten Statpendinten Hostpendinten Linkinten UserintenBit Field Rxpulseinttstat Rxthreshinttstat 31-8 Reserved TXPULSEINTTSTATn Txpulseinttstat Statpendintstat Statpendintstat Hostpendintstat Linkintstat Userintstat Tximax Rximax Mdio Version Register Version Field Descriptions Mdio Version Register VersionManagement Data Input/Output Mdio Registers Mdio Control Register Control Field Descriptions Mdio Control Register Control PHY Link Status Register Link PHY Acknowledge Status Register AlivePHY Acknowledge Status Register Alive Field Descriptions PHY Link Status Register Link Field Descriptions 31-2 Reserved Will clear the event and writing a 0 has no effect No Mdio user command complete event USERINTMASKED0 and USERINTMASKED1 correspond to USERACCESS0 W1S-0 Mdio User Command Complete Interrupt Mask Clear Register Mdio User Command Complete Interrupt Mask Clear Register Mdio User Access Register 0 USERACCESS0 Field Descriptions Mdio User Access Register 0 USERACCESS0 Linksel Linkintenb Mdio User PHY Select Register 0 USERPHYSEL0Phyadrmon Linksel Mdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User Access Register 1 USERACCESS1 Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1 Ethernet Media Access Controller Emac Registers Offset Acronym Register Description Network Statistics Registers Transmit Control Register Txcontrol Field Descriptions Transmit Identification and Version Register TxidverTransmit Control Register Txcontrol Txtdnch Transmit Teardown Register TxteardownTransmit Teardown Register Txteardown Field Descriptions Rxident Receive Identification and Version Register RxidverRxmajorver Rxminorver Rxmajorver Receive Teardown Register Rxteardown Receive Control Register RxcontrolReceive Control Register Rxcontrol Field Descriptions Receive Teardown Register Rxteardown Field Descriptions TX7PEND Transmit Interrupt Status Unmasked Register Txintstatraw Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register Txintstatmasked TX7MASK Transmit Interrupt Mask Set Register Txintmaskset Transmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register Txintmaskclear MAC End Of Interrupt Vector Register Maceoivector MAC Input Vector Register MacinvectorMAC Input Vector Register Macinvector Field Descriptions Statpend RX7PEND Receive Interrupt Status Unmasked Register Rxintstatraw Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register Rxintstatmasked RX7MASK Receive Interrupt Mask Set Register Rxintmaskset Receive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register Rxintmaskclear Hostpend Statpend MAC Interrupt Status Unmasked Register MacintstatrawMAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Mask Clear Register Macintmaskclear MAC Interrupt Mask Set Register MacintmasksetHostmask Statmask Hostmask Rxcmfen Rxpasscrc Rxqosen RxnochainRxcsfen Rxcefen Rxcafen Rxpromch Frames containing errors are filtered Receive multicast channel select RXCH7EN Receive Unicast Enable Set Register Rxunicastset Receive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register Rxunicastclear Receive Maximum Length Register Rxmaxlen Field Descriptions Receive Maximum Length Register RxmaxlenReceive Buffer Offset Register Rxbufferoffset Rxfilterthresh Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol Field Descriptions MAC Control Register Maccontrol Rxbufferflowen TxflowenLoopback Fullduplex MAC Status Register Macstatus Field Descriptions MAC Status Register Macstatus Rxqosact Fifo Control Register Fifocontrol Emulation Control Register EmcontrolEmulation Control Register Emcontrol Field Descriptions Fifo Control Register Fifocontrol Field Descriptions Soft Reset Register Softreset MAC Configuration Register MacconfigMAC Configuration Register Macconfig Field Descriptions Soft Reset Register Softreset Field Descriptions MAC Source Address High Bytes Register Macsrcaddrhi MAC Source Address Low Bytes Register Macsrcaddrlo MAC Hash Address Register 2 MACHASH2 MAC Hash Address Register 1 MACHASH1MAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 2 MACHASH2 Field Descriptions Back Off Test Register Bofftest Field Descriptions Back Off Test Register BofftestTransmit Pacing Algorithm Test Register Tpacetest Transmit Pause Timer Register Txpause Receive Pause Timer Register RxpauseReceive Pause Timer Register Rxpause Field Descriptions Transmit Pause Timer Register Txpause Field Descriptions MAC Address Low Bytes Register Macaddrlo Field Descriptions MAC Address Low Bytes Register MacaddrloValid Matchfilt Channel MACADDR0 MACADDR1 Valid MAC Index Register Macindex MAC Address High Bytes Register MacaddrhiMAC Index Register Macindex Field Descriptions MACADDR2 MACADDR3 MACADDR4 MACADDR5 TXnHDP Receive Channel 0-7 Completion Pointer Register RXnCP Transmit Channel 0-7 Completion Pointer Register TXnCP Good Receive Frames Register Rxgoodframes Network Statistics RegistersBroadcast Receive Frames Register Rxbcastframes Multicast Receive Frames Register Rxmcastframes Receive Alignment/Code Errors Register Rxaligncodeerrors Receive CRC Errors Register RxcrcerrorsPause Receive Frames Register Rxpauseframes Receive Oversized Frames Register Rxoversized Receive Undersized Frames Register Rxundersized Receive Jabber Frames Register RxjabberReceive Frame Fragments Register Rxfragments Filtered Receive Frames Register Rxfiltered Receive Octet Frames Register Rxoctets Receive QOS Filtered Frames Register RxqosfilteredGood Transmit Frames Register Txgoodframes Broadcast Transmit Frames Register Txbcastframes Deferred Transmit Frames Register Txdeferred Pause Transmit Frames Register TxpauseframesTransmit Collision Frames Register Txcollision Transmit Single Collision Frames Register Txsinglecoll Transmit Carrier Sense Errors Register Txcarriersense Transmit Underrun Error Register TxunderrunTransmit Late Collision Frames Register Txlatecoll Transmit Octet Frames Register Txoctets Submit Documentation Feedback Receive DMA Overruns Register Rxdmaoverruns Network Octet Frames Register Netoctets Appendix a Glossary Term Definition Physical Layer Definitions Reference Additions/Modifications/Deletions Document Revision History Rfid Products ApplicationsDSP