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48 | Transmit Interrupt Mask Set Register (TXINTMASKSET) | 92 |
49 | Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) | 93 |
50 | MAC Input Vector Register (MACINVECTOR) | 94 |
51 | MAC End Of Interrupt Vector Register (MACEOIVECTOR) | 94 |
52 | Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) | 95 |
53 | Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) | 96 |
54 | Receive Interrupt Mask Set Register (RXINTMASKSET) | 97 |
55 | Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) | 98 |
56 | MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) | 99 |
57 | MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) | 99 |
58 | MAC Interrupt Mask Set Register (MACINTMASKSET) | 100 |
59 | MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) | 100 |
60 | Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) | 101 |
61 | Receive Unicast Enable Set Register (RXUNICASTSET) | 104 |
62 | Receive Unicast Clear Register (RXUNICASTCLEAR) | 105 |
63 | Receive Maximum Length Register (RXMAXLEN) | 106 |
64 | Receive Buffer Offset Register (RXBUFFEROFFSET) | 106 |
65 | Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) | 107 |
66 | Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) | 107 |
67 | Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) | 108 |
68 | MAC Control Register (MACCONTROL) | 109 |
69 | MAC Status Register (MACSTATUS) | 111 |
70 | Emulation Control Register (EMCONTROL) | 113 |
71 | FIFO Control Register (FIFOCONTROL) | 113 |
72 | MAC Configuration Register (MACCONFIG) | 114 |
73 | Soft Reset Register (SOFTRESET) | 114 |
74 | MAC Source Address Low Bytes Register (MACSRCADDRLO) | 115 |
75 | MAC Source Address High Bytes Register (MACSRCADDRHI) | 115 |
76 | MAC Hash Address Register 1 (MACHASH1) | 116 |
77 | MAC Hash Address Register 2 (MACHASH2) | 116 |
78 | Back Off Random Number Generator Test Register (BOFFTEST) | 117 |
79 | Transmit Pacing Algorithm Test Register (TPACETEST) | 117 |
80 | Receive Pause Timer Register (RXPAUSE) | 118 |
81 | Transmit Pause Timer Register (TXPAUSE) | 118 |
82 | MAC Address Low Bytes Register (MACADDRLO) | 119 |
83 | MAC Address High Bytes Register (MACADDRHI) | 120 |
84 | MAC Index Register (MACINDEX) | 120 |
85 | Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) | 121 |
86 | Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) | 121 |
87 | Transmit Channel n Completion Pointer Register (TXnCP) | 122 |
88 | Receive Channel n Completion Pointer Register (RXnCP) | 122 |
89 | Statistics Register | 123 |
SPRUFI5B | List of Figures | 7 |
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