Texas Instruments TMS320DM36X manual Purpose of the Peripheral, Features

User's Guide

SPRUFI5B – March 2009 – Revised December 2010

Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)

1Introduction

This document provides a functional description of the Ethernet Media Access Controller (EMAC) and physical layer (PHY) device Management Data Input/Output (MDIO) module integrated in the device. Included are the features of the EMAC and MDIO modules, a discussion of their architecture and operation, how these modules connect to the outside world, and a description of the registers for each module.

The EMAC controls the flow of packet data from the system to the PHY. The MDIO module controls PHY configuration and status monitoring.

Both the EMAC and the MDIO modules interface to the system core through a custom interface that allows efficient data transmission and reception. This custom interface is referred to as the EMAC control module and is considered integral to the EMAC/MDIO peripheral.

1.1Purpose of the Peripheral

The EMAC module is used to move data between theDM36x DMSoC and another host connected to the same network, in compliance with the Ethernet protocol. The EMAC is controlled by the ARM CPU of the device; control by the DSP CPU is not supported.

1.2Features

The EMAC/MDIO has the following features:

•Synchronous 10/100 Mbps operation

•MII interface to the physical layer device (PHY)

•EMAC acts as DMA master to either internal or external device memory space

•Hardware error handling including CRC

•Eight receive channels with VLAN tag discrimination for receive quality-of-service (QOS) support

•Eight transmit channels with round-robin or fixed priority for transmit quality-of-service (QOS) support

•Ether-Stats and 802.3-Stats RMON statistics gathering

•Transmit CRC generation selectable on a per channel basis

•Broadcast frames selection for reception on a single channel

•Multicast frames selection for reception on a single channel

•Promiscuous receive mode frames selection for reception on a single channel (all frames, all good frames, short frames, error frames)

•Hardware flow control

•8K-byte local EMAC descriptor memory that allows the peripheral to operate on descriptors without affecting the CPU. The descriptor memory holds enough information to transfer up to 512 Ethernet packets without CPU intervention.

•Programmable interrupt logic permits the software driver to restrict the generation of back-to-back interrupts, which allows more work to be performed in a single call to the interrupt service routine.

•TI Adaptive Performance Optimization for improved half duplex performance

•Configurable receive address matching/filtering, receive FIFO depth, and transmit FIFO depth

•No-chain mode truncates frame to first buffer for network analysis applications

SPRUFI5B –March 2009 –Revised December 2010 Ethernet Media Access Controller (EMAC)/Management Data Input/Output 13

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