Texas Instruments TMS320DM36X manual MAC Control Register Maccontrol

www.ti.com Ethernet Media Access Controller (EMAC) Registers

5.29 MAC Control Register (MACCONTROL)

The MAC control register (MACCONTROL) is shown in Figure 68 and described in Table 66.

Figure 68. MAC Control Register (MACCONTROL)

31					18	17	16
			Reserved
			R-0
15	14	13	12	11	10	9	8

Reserved

RXOFFLENBLOCK

RXOWNERSHIP

RXFIFOFLOWEN

CMDIDLE

Rsvd

TXPTYPE

Reserved

R-0		R/W-0	R/W-0	R/W-0	R/W-0	R-0	R/W-0	R-0
7	6	5	4	3		2	1	0

Reserved

TXPACE

MIIEN

TXFLOWEN

RXBUFFERFLOWEN

Rsvd

LOOPBACK

FULLDUPLEX

R-0 R/W-0 R/W-0 R/W-0R/W-0R-0 R/W-0R/W-0

LEGEND: R = Read only; R/W = Read/Write; -n= value after reset

Table 66. MAC Control Register (MACCONTROL) Field Descriptions

Bit	Field	Value	Description
31-15	Reserved	0	Any writes to these bit(s) must always have a value of 0
14	RXOFFLENBLOCK		Receive offset/length word write block.
		0	Do not block the DMA writes to the receive buffer descriptor offset/buffer length word.
		1	Block all EMAC DMA controller writes to the receive buffer descriptor offset/buffer length
			words during packet processing. When this bit is set, the EMAC will never write the third word
			to any receive buffer descriptor.
13	RXOWNERSHIP		Receive ownership write bit value.
		0	EMAC writes the Receive ownership bit to 0 at the end of packet processing.
		1	EMAC writes the Receive ownership bit to 1 at the end of packet processing. If you do not use
			the ownership mechanism, you can set this mode to preclude the necessity of software having
			to set this bit each time the buffer descriptor is used.
12	RXFIFOFLOWEN		Receive FIFO flow control enable bit.
		0	Receive flow control is disabled. Full-duplex mode: no outgoing pause frames are sent.
		1	Receive flow control is enabled. Full-duplex mode: outgoing pause frames are sent when
			receive FIFO flow control is triggered.
11	CMDIDLE		Command Idle bit.
		0	Idle is not commanded.
		1	Idle is commanded (read the IDLE bit in the MACSTATUS register).
10	Reserved	0	Any writes to these bit(s) must always have a value of 0
9	TXPTYPE		Transmit queue priority type.
		0	The queue uses a round-robin scheme to select the next channel for transmission.
		1	The queue uses a fixed-priority (channel 7 is highest priority) scheme to select the next
			channel for transmission.
8-7	Reserved	0	Any writes to these bit(s) must always have a value of 0
6	TXPACE		Transmit pacing enable bit.
		0	Transmit pacing is disabled.
		1	Transmit pacing is enabled.
5	MIIEN		MII enable bit.
		0	MII RX and TX are held in reset.
		1	MII RX and TX are enabled for receive and transmit.

SPRUFI5B –March 2009 –Revised December 2010 Ethernet Media Access Controller (EMAC)/Management Data Input/Output 109

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