Texas Instruments TMS320DM36X specs

MDIO Registers

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4.10MDIO User Command Complete Interrupt Mask Clear Register

(USERINTMASKCLEAR)

The MDIO user command complete interrupt mask clear register (USERINTMASKCLEAR) is shown in Figure 35 and described in Table 32.

Figure 35. MDIO User Command Complete Interrupt Mask Clear Register

(USERINTMASKCLEAR)

31			16
	Reserved

	R-0
15	2	1	0

Reserved		USERINTMASKCLEAR

R-0			R/W1C-0

LEGEND: R = Read only; R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect; -n= value after reset

Table 32. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)

Field Descriptions

Bit	Field	Value	Description

31-2	Reserved	0	Reserved

1-0	USERINTMASKCLEAR	0-3h	MDIO user command complete interrupt mask clear for USERINTMASKED[1:0],
			respectively. Setting a bit to 1 will disable further user command complete interrupts
			for that particular USERACCESS register. USERINTMASKCLEAR[0] and
			USERINTMASKCLEAR[1] correspond to USERACCESS0 and USERACCESS1,
			respectively. Writing a 0 to this register has no effect.
		0	MDIO user command complete interrupts for the MDIO user access register n
			(USERACCESSn) are enabled.
		1	MDIO user command complete interrupts for the MDIO user access register n
			(USERACCESSn) are disabled.

78 Ethernet Media Access Controller (EMAC)/Management Data Input/Output SPRUFI5B –March 2009 –Revised December 2010

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Texas Instruments TMS320DM36X manual Mdio User Command Complete Interrupt Mask Clear Register

Contents

Users Guide Submit Documentation Feedback Mdio Registers Mdio Version Register Version Mdio Control Register Control Appendix a Appendix B List of Figures Transmit Interrupt Mask Set Register Txintmaskset List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Related Documentation From Texas Instruments Related Documentation From Texas Instruments Features Purpose of the Peripheral Functional Block Diagram Emac and Mdio Block Diagram Industry Standards Compliance Statement Clock ControlMII Clocking Signal Descriptions Memory MapMedia Independent Interface MII Connections Emac and Mdio Signals for MII Interface Signal Type DescriptionPin Multiplexing Ethernet Frame Description Ethernet Protocol OverviewEthernet Frame Format Field Bytes Description Packet Buffer Descriptors Ethernet’s Multiple Access ProtocolProgramming Interface Word Basic Descriptor Description Field Field Description Transmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Transmit Buffer Descriptor Format Example 1. Transmit Buffer Descriptor in C Structure Format Buffer Offset Next Descriptor PointerBuffer Pointer Buffer Length End of Queue EOQ Flag End of Packet EOP FlagOwnership Owner Flag Teardown Complete Tdowncmplt Flag Receive Buffer Descriptor Format Receive Buffer Descriptor Format Example 2. Receive Buffer Descriptor in C Structure Format Buffer Length CRC Error Crcerror Flag Code Error Codeerror FlagAlignment Error Alignerror Flag Jabber Flag Bus Arbiter Emac Control ModuleInternal Memory CPU Interrupt Control Transmit Pulse InterruptReceive Pulse Interrupt Receive Threshold Pulse Interrupt Miscellaneous Pulse InterruptInterrupt Pacing Mdio Clock Generator Mdio ModuleMdio Module Components Global PHY Detection and Link State Monitoring PHY Register User Access Active PHY MonitoringMdio Module Operational Overview Initializing the Mdio Module Writing Data To a PHY RegisterReading Data From a PHY Register Example of Mdio Register Access Code Example 3. Mdio Register Access Macros Receive DMA Engine Emac ModuleEmac Module Components Receive Fifo Receive Address Clock and Reset LogicMAC Receiver Transmit DMA Engine Emac Module Operational Overview Receive Control Media Independent Interface MIIData Reception Receive Inter-Frame Interval Collision-Based Receive Buffer Flow Control Ieee 802.3x-Based Receive Buffer Flow Control Adaptive Performance Optimization APO Transmit ControlCRC Insertion Interpacket-Gap IPG Enforcement Transmit Flow Control Speed, Duplex, and Pause Frame Support Receive DMA Host Configuration Packet Receive OperationReceive Channel Enabling Receive Address Matching Hardware Receive QOS Support Host Free Buffer Tracking Receive Channel TeardownReceive Frame Classification Promiscuous Receive Mode Receive Frame Treatment SummaryReceive Frame Treatment Receive Overrun Middle of Frame Overrun TreatmentMiddle of Frame Overrun Treatment Receive and Transmit Latency Transmit DMA Host ConfigurationPacket Transmit Operation Transmit Channel Teardown Reset Considerations Software Reset ConsiderationsTransfer Node Priority Enabling the EMAC/MDIO Peripheral Hardware Reset ConsiderationsInitialization Emac Control Module Initialization Example 4. Emac Control Module Initialization Code Mdio Module Initialization Example 5. Mdio Module Initialization Code Emac Module Initialization Receive Threshold Interrupts Interrupt SupportEmac Module Interrupt Events and Requests Transmit Packet Completion Interrupts Receive Packet Completion Interrupts Host Error Interrupt Statistics Interrupt Link Change Interrupt User Access Completion InterruptMdio Module Interrupt Events and Requests Proper Interrupt Processing Emulation Control Power ManagementEmulation Considerations Soft Free Description Acronym Register Description Emac Control Module RegistersSlave Vbus Bit Field Value Description Emac Control Module Emulation Control Register Cmemcontrol Emac Control Module Software Reset Register CmsoftresetSoftreset Soft Free Emac Control Module Interrupt Control Register Cmintctrl IntpaceenIntprescale Rxthreshen Rxpulseen Txpulseen Statpendinten Hostpendinten Linkinten Userinten Bit FieldStatpendinten Rxthreshinttstat Rxpulseinttstat Txpulseinttstat 31-8 Reserved TXPULSEINTTSTATn Statpendintstat Hostpendintstat Linkintstat Userintstat Statpendintstat Rximax Tximax Mdio Version Register Version Management Data Input/Output Mdio RegistersMdio Version Register Version Field Descriptions Mdio Control Register Control Mdio Control Register Control Field Descriptions PHY Acknowledge Status Register Alive Field Descriptions PHY Acknowledge Status Register AlivePHY Link Status Register Link PHY Link Status Register Link Field Descriptions 31-2 Reserved Will clear the event and writing a 0 has no effect No Mdio user command complete event USERINTMASKED0 and USERINTMASKED1 correspond to USERACCESS0 W1S-0 Mdio User Command Complete Interrupt Mask Clear Register Mdio User Command Complete Interrupt Mask Clear Register Mdio User Access Register 0 USERACCESS0 Mdio User Access Register 0 USERACCESS0 Field Descriptions Phyadrmon Mdio User PHY Select Register 0 USERPHYSEL0Linksel Linkintenb Linksel Mdio User Access Register 1 USERACCESS1 Mdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1 Ethernet Media Access Controller Emac Registers Offset Acronym Register Description Network Statistics Registers Transmit Identification and Version Register Txidver Transmit Control Register TxcontrolTransmit Control Register Txcontrol Field Descriptions Transmit Teardown Register Txteardown Transmit Teardown Register Txteardown Field DescriptionsTxtdnch Rxmajorver Rxminorver Receive Identification and Version Register RxidverRxident Rxmajorver Receive Control Register Rxcontrol Field Descriptions Receive Control Register RxcontrolReceive Teardown Register Rxteardown Receive Teardown Register Rxteardown Field Descriptions Transmit Interrupt Status Unmasked Register Txintstatraw TX7PEND Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Mask Set Register Txintmaskset TX7MASK Transmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register Txintmaskclear MAC Input Vector Register Macinvector Field Descriptions MAC Input Vector Register MacinvectorMAC End Of Interrupt Vector Register Maceoivector Statpend Receive Interrupt Status Unmasked Register Rxintstatraw RX7PEND Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Mask Set Register Rxintmaskset RX7MASK Receive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register Rxintmaskclear MAC Interrupt Status Unmasked Register Macintstatraw MAC Interrupt Status Masked Register MacintstatmaskedHostpend Statpend Hostmask Statmask MAC Interrupt Mask Set Register MacintmasksetMAC Interrupt Mask Clear Register Macintmaskclear Hostmask Rxcsfen Rxcefen Rxcafen Rxpasscrc Rxqosen RxnochainRxcmfen Rxpromch Frames containing errors are filtered Receive multicast channel select Receive Unicast Enable Set Register Rxunicastset RXCH7EN Receive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register Rxunicastclear Receive Maximum Length Register Rxmaxlen Receive Buffer Offset Register RxbufferoffsetReceive Maximum Length Register Rxmaxlen Field Descriptions Rxfilterthresh Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol MAC Control Register Maccontrol Field Descriptions Loopback TxflowenRxbufferflowen Fullduplex MAC Status Register Macstatus MAC Status Register Macstatus Field Descriptions Rxqosact Emulation Control Register Emcontrol Field Descriptions Emulation Control Register EmcontrolFifo Control Register Fifocontrol Fifo Control Register Fifocontrol Field Descriptions MAC Configuration Register Macconfig Field Descriptions MAC Configuration Register MacconfigSoft Reset Register Softreset Soft Reset Register Softreset Field Descriptions MAC Source Address Low Bytes Register Macsrcaddrlo MAC Source Address High Bytes Register Macsrcaddrhi MAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 1 MACHASH1MAC Hash Address Register 2 MACHASH2 MAC Hash Address Register 2 MACHASH2 Field Descriptions Back Off Test Register Bofftest Transmit Pacing Algorithm Test Register TpacetestBack Off Test Register Bofftest Field Descriptions Receive Pause Timer Register Rxpause Field Descriptions Receive Pause Timer Register RxpauseTransmit Pause Timer Register Txpause Transmit Pause Timer Register Txpause Field Descriptions Valid Matchfilt Channel MACADDR0 MACADDR1 MAC Address Low Bytes Register MacaddrloMAC Address Low Bytes Register Macaddrlo Field Descriptions Valid MAC Index Register Macindex Field Descriptions MAC Address High Bytes Register MacaddrhiMAC Index Register Macindex MACADDR2 MACADDR3 MACADDR4 MACADDR5 TXnHDP Transmit Channel 0-7 Completion Pointer Register TXnCP Receive Channel 0-7 Completion Pointer Register RXnCP Broadcast Receive Frames Register Rxbcastframes Network Statistics RegistersGood Receive Frames Register Rxgoodframes Multicast Receive Frames Register Rxmcastframes Pause Receive Frames Register Rxpauseframes Receive CRC Errors Register RxcrcerrorsReceive Alignment/Code Errors Register Rxaligncodeerrors Receive Oversized Frames Register Rxoversized Receive Frame Fragments Register Rxfragments Receive Jabber Frames Register RxjabberReceive Undersized Frames Register Rxundersized Filtered Receive Frames Register Rxfiltered Good Transmit Frames Register Txgoodframes Receive QOS Filtered Frames Register RxqosfilteredReceive Octet Frames Register Rxoctets Broadcast Transmit Frames Register Txbcastframes Transmit Collision Frames Register Txcollision Pause Transmit Frames Register TxpauseframesDeferred Transmit Frames Register Txdeferred Transmit Single Collision Frames Register Txsinglecoll Transmit Late Collision Frames Register Txlatecoll Transmit Underrun Error Register TxunderrunTransmit Carrier Sense Errors Register Txcarriersense Transmit Octet Frames Register Txoctets Submit Documentation Feedback Network Octet Frames Register Netoctets Receive DMA Overruns Register Rxdmaoverruns Appendix a Glossary Physical Layer Definitions Term Definition Document Revision History Reference Additions/Modifications/Deletions Products Applications DSPRfid