Texas Instruments TMS320DM36X specs

Ethernet Media Access Controller (EMAC) Registers

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5.28 Receive Channel 0-7 Free Buffer Count Register (RXnFREEBUFFER)

The receive channel 0-7 free buffer count register (RXnFREEBUFFER) is shown in Figure 67 and described in Table 65.

	Figure 67. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER)
31			16

			Reserved

			R-0
15			0

			RXnFREEBUF

			WI-0
LEGEND: R = Read only; WI = Write to increment; -n= value after reset
	Table 65. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) Field Descriptions

Bit	Field	Value	Description

31-16	Reserved	0	Reserved

15-0	RXnFREEBUF	0-FFh	Receive free buffer count. These bits contain the count of free buffers available. The
			RXFILTERTHRESH value is compared with this field to determine if low priority frames should be
			filtered. The RXnFLOWTHRESH value is compared with this field to determine if receive flow
			control should be issued against incoming packets (if enabled). This is a write-to-increment field.
			This field rolls over to 0 on overflow.
			If hardware flow control or QOS is used, the host must initialize this field to the number of available
			buffers (one register per channel). The EMAC decrements the associated channel register for each
			received frame by the number of buffers in the received frame. The host must write this field with
			the number of buffers that have been freed due to host processing.

108 Ethernet Media Access Controller (EMAC)/Management Data Input/Output SPRUFI5B –March 2009 –Revised December 2010

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Texas Instruments TMS320DM36X manual Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER

Contents

Users Guide Submit Documentation Feedback Mdio Registers Mdio Version Register Version Mdio Control Register Control Appendix a Appendix B List of Figures Transmit Interrupt Mask Set Register Txintmaskset List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Related Documentation From Texas Instruments Related Documentation From Texas Instruments Features Purpose of the Peripheral Functional Block Diagram Emac and Mdio Block Diagram Industry Standards Compliance Statement Clock ControlMII Clocking Signal Descriptions Memory MapMedia Independent Interface MII Connections Emac and Mdio Signals for MII Interface Signal Type DescriptionPin Multiplexing Ethernet Protocol Overview Ethernet Frame FormatEthernet Frame Description Field Bytes Description Ethernet’s Multiple Access Protocol Programming InterfacePacket Buffer Descriptors Word Basic Descriptor Description Field Field Description Transmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Transmit Buffer Descriptor Format Example 1. Transmit Buffer Descriptor in C Structure Format Next Descriptor Pointer Buffer PointerBuffer Offset Buffer Length End of Packet EOP Flag Ownership Owner FlagEnd of Queue EOQ Flag Teardown Complete Tdowncmplt Flag Receive Buffer Descriptor Format Receive Buffer Descriptor Format Example 2. Receive Buffer Descriptor in C Structure Format Buffer Length Code Error Codeerror Flag Alignment Error Alignerror FlagCRC Error Crcerror Flag Jabber Flag Emac Control Module Internal MemoryBus Arbiter CPU Interrupt Control Transmit Pulse InterruptReceive Pulse Interrupt Receive Threshold Pulse Interrupt Miscellaneous Pulse InterruptInterrupt Pacing Mdio Module Mdio Module ComponentsMdio Clock Generator Global PHY Detection and Link State Monitoring PHY Register User Access Active PHY MonitoringMdio Module Operational Overview Initializing the Mdio Module Writing Data To a PHY RegisterReading Data From a PHY Register Example of Mdio Register Access Code Example 3. Mdio Register Access Macros Emac Module Emac Module ComponentsReceive DMA Engine Receive Fifo Clock and Reset Logic MAC ReceiverReceive Address Transmit DMA Engine Emac Module Operational Overview Media Independent Interface MII Data ReceptionReceive Control Receive Inter-Frame Interval Collision-Based Receive Buffer Flow Control Ieee 802.3x-Based Receive Buffer Flow Control Transmit Control CRC InsertionAdaptive Performance Optimization APO Interpacket-Gap IPG Enforcement Transmit Flow Control Speed, Duplex, and Pause Frame Support Receive DMA Host Configuration Packet Receive OperationReceive Channel Enabling Receive Address Matching Hardware Receive QOS Support Host Free Buffer Tracking Receive Channel TeardownReceive Frame Classification Promiscuous Receive Mode Receive Frame Treatment SummaryReceive Frame Treatment Receive Overrun Middle of Frame Overrun TreatmentMiddle of Frame Overrun Treatment Transmit DMA Host Configuration Packet Transmit OperationReceive and Transmit Latency Transmit Channel Teardown Reset Considerations Software Reset ConsiderationsTransfer Node Priority Hardware Reset Considerations InitializationEnabling the EMAC/MDIO Peripheral Emac Control Module Initialization Example 4. Emac Control Module Initialization Code Mdio Module Initialization Example 5. Mdio Module Initialization Code Emac Module Initialization Interrupt Support Emac Module Interrupt Events and RequestsReceive Threshold Interrupts Transmit Packet Completion Interrupts Receive Packet Completion Interrupts Host Error Interrupt Statistics Interrupt User Access Completion Interrupt Mdio Module Interrupt Events and RequestsLink Change Interrupt Proper Interrupt Processing Power Management Emulation ConsiderationsEmulation Control Soft Free Description Emac Control Module Registers Slave VbusAcronym Register Description Bit Field Value Description Emac Control Module Software Reset Register Cmsoftreset SoftresetEmac Control Module Emulation Control Register Cmemcontrol Soft Free Emac Control Module Interrupt Control Register Cmintctrl IntpaceenIntprescale Rxthreshen Rxpulseen Txpulseen Statpendinten Hostpendinten Linkinten Userinten Bit FieldStatpendinten Rxthreshinttstat Rxpulseinttstat Txpulseinttstat 31-8 Reserved TXPULSEINTTSTATn Statpendintstat Hostpendintstat Linkintstat Userintstat Statpendintstat Rximax Tximax Mdio Version Register Version Management Data Input/Output Mdio RegistersMdio Version Register Version Field Descriptions Mdio Control Register Control Mdio Control Register Control Field Descriptions PHY Acknowledge Status Register Alive PHY Link Status Register LinkPHY Acknowledge Status Register Alive Field Descriptions PHY Link Status Register Link Field Descriptions 31-2 Reserved Will clear the event and writing a 0 has no effect No Mdio user command complete event USERINTMASKED0 and USERINTMASKED1 correspond to USERACCESS0 W1S-0 Mdio User Command Complete Interrupt Mask Clear Register Mdio User Command Complete Interrupt Mask Clear Register Mdio User Access Register 0 USERACCESS0 Mdio User Access Register 0 USERACCESS0 Field Descriptions Mdio User PHY Select Register 0 USERPHYSEL0 Linksel LinkintenbPhyadrmon Linksel Mdio User Access Register 1 USERACCESS1 Mdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1 Ethernet Media Access Controller Emac Registers Offset Acronym Register Description Network Statistics Registers Transmit Identification and Version Register Txidver Transmit Control Register TxcontrolTransmit Control Register Txcontrol Field Descriptions Transmit Teardown Register Txteardown Transmit Teardown Register Txteardown Field DescriptionsTxtdnch Receive Identification and Version Register Rxidver RxidentRxmajorver Rxminorver Rxmajorver Receive Control Register Rxcontrol Receive Teardown Register RxteardownReceive Control Register Rxcontrol Field Descriptions Receive Teardown Register Rxteardown Field Descriptions Transmit Interrupt Status Unmasked Register Txintstatraw TX7PEND Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Mask Set Register Txintmaskset TX7MASK Transmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register Txintmaskclear MAC Input Vector Register Macinvector MAC End Of Interrupt Vector Register MaceoivectorMAC Input Vector Register Macinvector Field Descriptions Statpend Receive Interrupt Status Unmasked Register Rxintstatraw RX7PEND Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Mask Set Register Rxintmaskset RX7MASK Receive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register Rxintmaskclear MAC Interrupt Status Unmasked Register Macintstatraw MAC Interrupt Status Masked Register MacintstatmaskedHostpend Statpend MAC Interrupt Mask Set Register Macintmaskset MAC Interrupt Mask Clear Register MacintmaskclearHostmask Statmask Hostmask Rxpasscrc Rxqosen Rxnochain RxcmfenRxcsfen Rxcefen Rxcafen Rxpromch Frames containing errors are filtered Receive multicast channel select Receive Unicast Enable Set Register Rxunicastset RXCH7EN Receive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register Rxunicastclear Receive Maximum Length Register Rxmaxlen Receive Buffer Offset Register RxbufferoffsetReceive Maximum Length Register Rxmaxlen Field Descriptions Rxfilterthresh Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol MAC Control Register Maccontrol Field Descriptions Txflowen RxbufferflowenLoopback Fullduplex MAC Status Register Macstatus MAC Status Register Macstatus Field Descriptions Rxqosact Emulation Control Register Emcontrol Fifo Control Register FifocontrolEmulation Control Register Emcontrol Field Descriptions Fifo Control Register Fifocontrol Field Descriptions MAC Configuration Register Macconfig Soft Reset Register SoftresetMAC Configuration Register Macconfig Field Descriptions Soft Reset Register Softreset Field Descriptions MAC Source Address Low Bytes Register Macsrcaddrlo MAC Source Address High Bytes Register Macsrcaddrhi MAC Hash Address Register 1 MACHASH1 MAC Hash Address Register 2 MACHASH2MAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 2 MACHASH2 Field Descriptions Back Off Test Register Bofftest Transmit Pacing Algorithm Test Register TpacetestBack Off Test Register Bofftest Field Descriptions Receive Pause Timer Register Rxpause Transmit Pause Timer Register TxpauseReceive Pause Timer Register Rxpause Field Descriptions Transmit Pause Timer Register Txpause Field Descriptions MAC Address Low Bytes Register Macaddrlo MAC Address Low Bytes Register Macaddrlo Field DescriptionsValid Matchfilt Channel MACADDR0 MACADDR1 Valid MAC Address High Bytes Register Macaddrhi MAC Index Register MacindexMAC Index Register Macindex Field Descriptions MACADDR2 MACADDR3 MACADDR4 MACADDR5 TXnHDP Transmit Channel 0-7 Completion Pointer Register TXnCP Receive Channel 0-7 Completion Pointer Register RXnCP Network Statistics Registers Good Receive Frames Register RxgoodframesBroadcast Receive Frames Register Rxbcastframes Multicast Receive Frames Register Rxmcastframes Receive CRC Errors Register Rxcrcerrors Receive Alignment/Code Errors Register RxaligncodeerrorsPause Receive Frames Register Rxpauseframes Receive Oversized Frames Register Rxoversized Receive Jabber Frames Register Rxjabber Receive Undersized Frames Register RxundersizedReceive Frame Fragments Register Rxfragments Filtered Receive Frames Register Rxfiltered Receive QOS Filtered Frames Register Rxqosfiltered Receive Octet Frames Register RxoctetsGood Transmit Frames Register Txgoodframes Broadcast Transmit Frames Register Txbcastframes Pause Transmit Frames Register Txpauseframes Deferred Transmit Frames Register TxdeferredTransmit Collision Frames Register Txcollision Transmit Single Collision Frames Register Txsinglecoll Transmit Underrun Error Register Txunderrun Transmit Carrier Sense Errors Register TxcarriersenseTransmit Late Collision Frames Register Txlatecoll Transmit Octet Frames Register Txoctets Submit Documentation Feedback Network Octet Frames Register Netoctets Receive DMA Overruns Register Rxdmaoverruns Appendix a Glossary Physical Layer Definitions Term Definition Document Revision History Reference Additions/Modifications/Deletions Products Applications DSPRfid