Txpulseen | Texas Instruments TMS320DM36X guide

EMAC Control Module Registers

www.ti.com

3.7EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN)

The transmit interrupt enable register (CMTXINTEN) is shown in Figure 18 and described in Table 14.

Figure 18. EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN)

31				16
	Reserved

		R-0
15	8	7		0

Reserved				TXPULSEEN

R-0				R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 14. EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN)

Field Descriptions

Bit	Field	Value	Description

31-8	Reserved	0	Reserved

7-0	TXPULSEEN[n]		Transmit interrupt (TXPENDn) enable. Each bit controls the corresponding channel n transmit
			interrupt.
			Bit n = 0,channel n transmit interrupt (TXPENDn) is disabled.
			Bit n = 1, channel n transmit interrupt (TXPENDn) is enabled.

64 Ethernet Media Access Controller (EMAC)/Management Data Input/Output SPRUFI5B –March 2009 –Revised December 2010

(MDIO)	Submit Documentation Feedback

© 2009–2010, Texas Instruments Incorporated

Image 64

Texas Instruments TMS320DM36X manual Txpulseen

Contents

Users Guide Submit Documentation Feedback Mdio Registers Mdio Version Register Version Mdio Control Register Control Appendix a Appendix B List of Figures Transmit Interrupt Mask Set Register Txintmaskset List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Related Documentation From Texas Instruments Related Documentation From Texas Instruments Features Purpose of the Peripheral Functional Block Diagram Emac and Mdio Block Diagram Clock Control Industry Standards Compliance StatementMII Clocking Memory Map Signal DescriptionsMedia Independent Interface MII Connections Signal Type Description Emac and Mdio Signals for MII InterfacePin Multiplexing Ethernet Protocol Overview Ethernet Frame FormatEthernet Frame Description Field Bytes Description Ethernet’s Multiple Access Protocol Programming InterfacePacket Buffer Descriptors Word Basic Descriptor Description Field Field Description Transmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Transmit Buffer Descriptor Format Example 1. Transmit Buffer Descriptor in C Structure Format Next Descriptor Pointer Buffer PointerBuffer Offset Buffer Length End of Packet EOP Flag Ownership Owner FlagEnd of Queue EOQ Flag Teardown Complete Tdowncmplt Flag Receive Buffer Descriptor Format Receive Buffer Descriptor Format Example 2. Receive Buffer Descriptor in C Structure Format Buffer Length Code Error Codeerror Flag Alignment Error Alignerror FlagCRC Error Crcerror Flag Jabber Flag Emac Control Module Internal MemoryBus Arbiter CPU Transmit Pulse Interrupt Interrupt ControlReceive Pulse Interrupt Miscellaneous Pulse Interrupt Receive Threshold Pulse InterruptInterrupt Pacing Mdio Module Mdio Module ComponentsMdio Clock Generator Global PHY Detection and Link State Monitoring Active PHY Monitoring PHY Register User AccessMdio Module Operational Overview Writing Data To a PHY Register Initializing the Mdio ModuleReading Data From a PHY Register Example of Mdio Register Access Code Example 3. Mdio Register Access Macros Emac Module Emac Module ComponentsReceive DMA Engine Receive Fifo Clock and Reset Logic MAC ReceiverReceive Address Transmit DMA Engine Emac Module Operational Overview Media Independent Interface MII Data ReceptionReceive Control Receive Inter-Frame Interval Collision-Based Receive Buffer Flow Control Ieee 802.3x-Based Receive Buffer Flow Control Transmit Control CRC InsertionAdaptive Performance Optimization APO Interpacket-Gap IPG Enforcement Transmit Flow Control Speed, Duplex, and Pause Frame Support Packet Receive Operation Receive DMA Host ConfigurationReceive Channel Enabling Receive Address Matching Hardware Receive QOS Support Receive Channel Teardown Host Free Buffer TrackingReceive Frame Classification Receive Frame Treatment Summary Promiscuous Receive ModeReceive Frame Treatment Middle of Frame Overrun Treatment Receive OverrunMiddle of Frame Overrun Treatment Transmit DMA Host Configuration Packet Transmit OperationReceive and Transmit Latency Transmit Channel Teardown Software Reset Considerations Reset ConsiderationsTransfer Node Priority Hardware Reset Considerations InitializationEnabling the EMAC/MDIO Peripheral Emac Control Module Initialization Example 4. Emac Control Module Initialization Code Mdio Module Initialization Example 5. Mdio Module Initialization Code Emac Module Initialization Interrupt Support Emac Module Interrupt Events and RequestsReceive Threshold Interrupts Transmit Packet Completion Interrupts Receive Packet Completion Interrupts Host Error Interrupt Statistics Interrupt User Access Completion Interrupt Mdio Module Interrupt Events and RequestsLink Change Interrupt Proper Interrupt Processing Power Management Emulation ConsiderationsEmulation Control Soft Free Description Emac Control Module Registers Slave VbusAcronym Register Description Bit Field Value Description Emac Control Module Software Reset Register Cmsoftreset SoftresetEmac Control Module Emulation Control Register Cmemcontrol Soft Free Intpaceen Emac Control Module Interrupt Control Register CmintctrlIntprescale Rxthreshen Rxpulseen Txpulseen Bit Field Statpendinten Hostpendinten Linkinten UserintenStatpendinten Rxthreshinttstat Rxpulseinttstat Txpulseinttstat 31-8 Reserved TXPULSEINTTSTATn Statpendintstat Hostpendintstat Linkintstat Userintstat Statpendintstat Rximax Tximax Management Data Input/Output Mdio Registers Mdio Version Register VersionMdio Version Register Version Field Descriptions Mdio Control Register Control Mdio Control Register Control Field Descriptions PHY Acknowledge Status Register Alive PHY Link Status Register LinkPHY Acknowledge Status Register Alive Field Descriptions PHY Link Status Register Link Field Descriptions 31-2 Reserved Will clear the event and writing a 0 has no effect No Mdio user command complete event USERINTMASKED0 and USERINTMASKED1 correspond to USERACCESS0 W1S-0 Mdio User Command Complete Interrupt Mask Clear Register Mdio User Command Complete Interrupt Mask Clear Register Mdio User Access Register 0 USERACCESS0 Mdio User Access Register 0 USERACCESS0 Field Descriptions Mdio User PHY Select Register 0 USERPHYSEL0 Linksel LinkintenbPhyadrmon Linksel Mdio User Access Register 1 USERACCESS1 Mdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1 Ethernet Media Access Controller Emac Registers Offset Acronym Register Description Network Statistics Registers Transmit Control Register Txcontrol Transmit Identification and Version Register TxidverTransmit Control Register Txcontrol Field Descriptions Transmit Teardown Register Txteardown Field Descriptions Transmit Teardown Register TxteardownTxtdnch Receive Identification and Version Register Rxidver RxidentRxmajorver Rxminorver Rxmajorver Receive Control Register Rxcontrol Receive Teardown Register RxteardownReceive Control Register Rxcontrol Field Descriptions Receive Teardown Register Rxteardown Field Descriptions Transmit Interrupt Status Unmasked Register Txintstatraw TX7PEND Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Mask Set Register Txintmaskset TX7MASK Transmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register Txintmaskclear MAC Input Vector Register Macinvector MAC End Of Interrupt Vector Register MaceoivectorMAC Input Vector Register Macinvector Field Descriptions Statpend Receive Interrupt Status Unmasked Register Rxintstatraw RX7PEND Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Mask Set Register Rxintmaskset RX7MASK Receive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register Rxintmaskclear MAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Status Unmasked Register MacintstatrawHostpend Statpend MAC Interrupt Mask Set Register Macintmaskset MAC Interrupt Mask Clear Register MacintmaskclearHostmask Statmask Hostmask Rxpasscrc Rxqosen Rxnochain RxcmfenRxcsfen Rxcefen Rxcafen Rxpromch Frames containing errors are filtered Receive multicast channel select Receive Unicast Enable Set Register Rxunicastset RXCH7EN Receive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register Rxunicastclear Receive Buffer Offset Register Rxbufferoffset Receive Maximum Length Register RxmaxlenReceive Maximum Length Register Rxmaxlen Field Descriptions Rxfilterthresh Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol MAC Control Register Maccontrol Field Descriptions Txflowen RxbufferflowenLoopback Fullduplex MAC Status Register Macstatus MAC Status Register Macstatus Field Descriptions Rxqosact Emulation Control Register Emcontrol Fifo Control Register FifocontrolEmulation Control Register Emcontrol Field Descriptions Fifo Control Register Fifocontrol Field Descriptions MAC Configuration Register Macconfig Soft Reset Register SoftresetMAC Configuration Register Macconfig Field Descriptions Soft Reset Register Softreset Field Descriptions MAC Source Address Low Bytes Register Macsrcaddrlo MAC Source Address High Bytes Register Macsrcaddrhi MAC Hash Address Register 1 MACHASH1 MAC Hash Address Register 2 MACHASH2MAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 2 MACHASH2 Field Descriptions Transmit Pacing Algorithm Test Register Tpacetest Back Off Test Register BofftestBack Off Test Register Bofftest Field Descriptions Receive Pause Timer Register Rxpause Transmit Pause Timer Register TxpauseReceive Pause Timer Register Rxpause Field Descriptions Transmit Pause Timer Register Txpause Field Descriptions MAC Address Low Bytes Register Macaddrlo MAC Address Low Bytes Register Macaddrlo Field DescriptionsValid Matchfilt Channel MACADDR0 MACADDR1 Valid MAC Address High Bytes Register Macaddrhi MAC Index Register MacindexMAC Index Register Macindex Field Descriptions MACADDR2 MACADDR3 MACADDR4 MACADDR5 TXnHDP Transmit Channel 0-7 Completion Pointer Register TXnCP Receive Channel 0-7 Completion Pointer Register RXnCP Network Statistics Registers Good Receive Frames Register RxgoodframesBroadcast Receive Frames Register Rxbcastframes Multicast Receive Frames Register Rxmcastframes Receive CRC Errors Register Rxcrcerrors Receive Alignment/Code Errors Register RxaligncodeerrorsPause Receive Frames Register Rxpauseframes Receive Oversized Frames Register Rxoversized Receive Jabber Frames Register Rxjabber Receive Undersized Frames Register RxundersizedReceive Frame Fragments Register Rxfragments Filtered Receive Frames Register Rxfiltered Receive QOS Filtered Frames Register Rxqosfiltered Receive Octet Frames Register RxoctetsGood Transmit Frames Register Txgoodframes Broadcast Transmit Frames Register Txbcastframes Pause Transmit Frames Register Txpauseframes Deferred Transmit Frames Register TxdeferredTransmit Collision Frames Register Txcollision Transmit Single Collision Frames Register Txsinglecoll Transmit Underrun Error Register Txunderrun Transmit Carrier Sense Errors Register TxcarriersenseTransmit Late Collision Frames Register Txlatecoll Transmit Octet Frames Register Txoctets Submit Documentation Feedback Network Octet Frames Register Netoctets Receive DMA Overruns Register Rxdmaoverruns Appendix a Glossary Physical Layer Definitions Term Definition Document Revision History Reference Additions/Modifications/Deletions DSP Products ApplicationsRfid