Series resistance, Signal Description | Toshiba MK6017MAP instruction

360014937

10.3.4 Series resistance

Each signal has its own series resistance.

SIGNAL	SERIAL RESISTANCE VALUE
-DIOR	82Ω
-HDMARDY
HSTROBE

-DIOW	82Ω
STOP

-CS0, -CS1	82Ω
DA0,DA1,DA2	82Ω
-DMACK	82Ω
DMARQ	22Ω
INTRQ	22Ω
IORDY	22Ω
-DDMARDY
DSTROBE

DD０～DD15	33Ω

10.3.5 Signal Description

SIGNAL	DIR.	PIN	DESCRIPTION
- RESET	O (*1)	1	Reset signal from the host system; It shall be active low when system is
			powered-up or when voltage fault is detected.
DD 15- 0	I/O	18- 3	16 bit bi- directional data bus between the host system and the drive. All 16 bits
			are used for data transfer in the data register. The lower 8 bits, HD0- HD7, are
			used for the other register and ECC access.
KEY	N/C	20	Pin position 20 has no connection pin, clipped on the drive and plugged on the
			cable in order to ensure correct orientation of the cable and to avoid wrong
			insertion.
DMARQ	I	21	DMA request signal is set by the drive to indicate that the DMA data transfer is
			ready. The direction of the data transfer is controlled by write/read strobe signal
			(HOST IOW or HOST IOR). This signal is used on a hand shake manner with -
			DMACK.
- DIOW	O	23	Write strobe. The rising clocks data from the host data bus, HD0 through HD15 to
STOP			a register or data register of the drive.
			Stop signal used by the host after the completion of Ultra DMA Burst.
- DIOR	O	25	Read strobe. When active low, this signal enables data from a register or the data
			of the drive onto the host data bus, HD0 through HD15. The rising edge of
			-HOST IOR latches on the data on the bus from the drive.
-HDMARDY			This signal is for reporting the drive that the host system is ready to accept Ultra
			DMA data.
HSTROBE			Strobe. HSTROBE indicates that the host transfers ULTRA DMA data. The rising
			edge and the falling edge of HSTROBE enable the drive to latch the data.
IORDY	I	27	IORDY reports host that the BUS is available.
-DDMARDY			-DDMARDY is asserted to indicate that the drive is ready to receive the Ultra DMA
			data.
DSTROBE			Strobe. DSTROBE is asserted to indicate that the drive transfers Ultra DMA data.
			The rising edge and falling edge of DSTROBE enable the host to latch the data.

Copyright © 2000 Toshiba corporation. All rights reserved.

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Toshiba MK6017MAP manual Series resistance, Signal Description

Contents

Toshiba STGE.PER ContentsREV Revised Ｓａｆｅｔｙ Usage Restrictions Safety Copyright 2000 Toshiba corporation. All rights reserved 506 Table of Contents Security SET Password Protocol Table of Figures Scope Copyright 2000 Toshiba corporation. All rights reserved 512 KEY Features Basic Specification Performance Energy Consumption Efficiency Power ConsumptionPower Sequence Supply Voltage Mounting Instructions DimensionWeight Drive Orientation Screwing Installation MK6017MAP Dimensions MK6017MAP Mounting Recommendation Shock Temperature and HumidityTemperature Vibration Safety Standards Acoustics （Sound Power ）Altitude Product Life Error RatePreventive Maintenance PM Mean Time to Failure Mttf Load/Unload Cabling Interface ConnectorCable Output Electrical specificationDC input/output Characteristics 10.2.2.1 Input Cable length and capacitance ATA interface connector Interface connector Ground Reserved Pin AssignmentPdiag ／-CBLID Dasp Ground Dasp Signal Treatment Series resistance Signal Description Copyright 2000 Toshiba corporation. All rights reserved 532 Program I/O Write Timing Host Interface Timing Program I/O Read Timing Single Word DMA Write Timing ATA-2 Specifications Single Word DMA Read Timing ATA-2 Specification Multiword DMA Write Timing ATA/ATAPI-5 Specifications Multiword DMA Read Timing Hdmardy Ultra DMA Timing Sustained Ultra DMA data in burst CRC Device terminating an Ultra DMA data in burst Host terminating an Ultra DMA data in burst Ddmardy Initiating an Ultra DMA data out burst Sustained Ultra DMA data out burst Host terminating an Ultra DMA data out burst Device terminating an Ultra DMA data out burst ATA/ATAPI specifications Grounding Reset Timing 1 Register map Address Decoding Register Description Error Register Security commandsOperational Mode Initialize Device Parameters command Diagnostic ModeSmart command Disk Access command Cylinder High Registers Smart commandsSector Number Register Cylinder Low Registers DEV HS3 HS2 HS1 HS0 Device/Head Register BSY Drdy DSC3 DRQ Corr IDX ERR Status Register Command Register Command Code Srst IEN Alternate Status RegisterDevice Control Register Device Address register4 Command Descriptions Recalibrate5 1xh Nop 00hFlush Cache E7h Read Long6 22h/23h Read Sector 20h/21hWrite Sector 30h/31h Read Verify 40h Write Long7 32h/33hWrite Verify8 3Ch Format Track 50h Seek 7xh Execute Diagnostics 90hToshiba Specific Initialize Device Parameters 91h Read Multiple C4h Write Multiple C5h Read DMA C8h/C9h Set Multiple Mode C6h Write DMA CAh/CBh SC=X Power Control ExhStand-by Immediate E0/94 Idle Immediate E1/95 Sleep E6/99 Check Power Mode E5/98Stand-by E2/96 Idle E3/97 Write Buffer E8h Read Buffer E4h Identify Device ECh Hex Word Description 360014937 2 Identify Information 360014937 3 Identify Information 360014937 4 Identify Information =ATA Toshiba MK6017MAP MK6017MAP Copyright 2000 Toshiba corporation. All rights reserved 581 Copyright 2000 Toshiba corporation. All rights reserved 582 Copyright 2000 Toshiba corporation. All rights reserved 583 Timer Actual Value Copyright 2000 Toshiba corporation. All rights reserved 585 Read Native Max Address F8h Set Max Address F9h Features FT register defines following selections Set Features EFh Security Set Password information Security SET Password F1h Security Erase Prepare F3h Security Unlock F2h Security Freeze Lock F5h Security Erase Unit F4h F6h Security Disable Password Smart Function Set Smart Read Attribute values 10.8.33.1 Attribute Name Value Definition Copyright 2000 Toshiba corporation. All rights reserved 596 Smart Read Attribute thresholds 10.8.33.2 10.8.33.4 Smart Save Attribute Values Smart Enable Disable Attribute Autosave 10.8.33.5 Smart Execute Off-line Immediate Off-line mode Captive mode Register Command CodeRegister Setting Normal Completion 10.8.33.6 Command data structure Error data structure Self-test log sector Self-test index 10.8.33.7 Smart Write Log Sector 10.8.33.9 Smart Disable Operations Smart Enable Operations Smart Return Status Smart Enable/Disable Automatic Off-line Initial setting of the user password Security mode default setting Unlock Security mode operation from power-onUnit Password lost Command Table Attributes Smart function default settingAttributes values Active Idle Adaptive Power Mode ControlLow Power Idle Performance Idle Register Power on Hardware Reset Software Reset Reset LOW Master/Slave ConfigurationHigh Automatic Write Reallocation Cache MemoryCache Operations Protocol Commands for this class are PIO data in commands PIO data out protocol PIO data out commands Non-data protocol Non-data commands DMA data transfer commands Ultra DMA Copyright 2000 Toshiba corporation. All rights reserved 624 = DD3 XOR CRCOUT12 = DD0 XOR CRCOUT15= DD1 XOR CRCOUT14 = DD2 XOR CRCOUT13 Other timings Function and Intervals Timeout