Intel 82555 manual LED Pins, External Bias Pins

Page 14

82555 — Networking Silicon

Symbol

Pin

Type

Name and Function

 

 

 

 

 

 

 

 

TXRDY

4

O

This pin is multiplexed and can be used for one of the following:

(TOUT)

 

 

Transmit Ready. If full duplex and PHY Base (Bay Technologies) flow control

 

 

 

modes are enabled, the TXRDY signal enables transmission while it is

 

 

 

asserted.

 

 

 

TOUT. When the Test Enable signal is activated, this signal functions as the

 

 

 

Test Output port.

 

 

 

 

FDX_N

5

I/O

Full Duplex. In DTE (adapter) mode, this active low output signal reports the

 

 

 

result of the duplex configuration to the MAC. This pin can also operate as

 

 

 

the LED driver and will be an active low for all technologies.

 

 

 

In repeater mode, this signal is used for Auto-Negotiation advertisement to

 

 

 

the 82555’s link partner and activates the PHY Base (Bay Technologies) flow

 

 

 

control if 100BASE-TX full duplex is the highest common technology between

 

 

 

the 82555 and its link partner.

 

 

 

 

3.6LED Pins

Symbol

Pin

Type

Name and Function

 

 

 

 

 

 

 

 

ACTLED

12

O

Activity LED. This signal indicates either transmit or receive activity. When

 

 

 

activity is present, the ACTLED is on. When no activity is present, the

 

 

 

ACTLED is off.

 

 

 

 

LILED

11

O

Link Integrity LED. This signal indicates the link integrity. If a valid link is

 

 

 

present in either 10 Mbps or 100 Mbps, the LILED is on; and if an invalid link

 

 

 

is preset, LILED is off.

 

 

 

For a combination design board, the LILED should be connected to the TX

 

 

 

technology LED.

 

 

 

 

SPEED-

13

O

Speed LED

LED

 

 

This signal is used to indicate the speed of operation. For 100 Mbps, the

 

 

 

 

 

 

SPEEDLED will be on; and for 10 Mbps, the SPEEDLED will be off.

 

 

 

 

3.7External Bias Pins

Symbol

Pin

Type

Name and Function

 

 

 

 

 

 

 

 

RBIAS100

44

B

Bias Reference Resistor 100. A 634 Ω resistor should be connected from

 

 

 

this pin to ground.

 

 

 

 

RBIAS10

43

B

Bias Reference Resistor 10. A 768 Ω resistor should be connected from

 

 

 

this pin to ground.

 

 

 

 

PD1

42

I

Pull Down One. A 10 KΩ resistor should be connected from this pin to

 

 

 

ground.

 

 

 

 

PD2

100

I

Pull Down One. A 1 KΩ resistor should be connected from this pin to

 

 

 

ground.

 

 

 

 

Note: The resistor values described for the external bias pins are only recommended values and may require to be fine tuned for various designs.

10

Datasheet

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Contents Product Features 82555 10/100 Mbps LAN Physical Layer InterfaceNetworking Silicon Revision DescriptionContents Repeater Mode Compliance to Industry Standards IntroductionFunctional Overview Networking Silicon 100 Mbps Mode Architectural Overview10 Mbps Mode MII TX InterfaceMedia Independent Interface MII Yes Transmit Error From RICRepeater mode only Pin Definitions Pin Numbers and LabelsMedia Independent Interface MII Pins Clock PinsTwisted Pair Ethernet TPE Pins Pin TypesMedia Access Control/Repeater Interface Control Pins LED Pins External Bias PinsMiscellaneous Control Pins VSS Power and Ground PinsVCC 100BASE-TX Transmit Clock Generation 100BASE-TX Adapter Mode OperationSymbol 5B Symbol Code 4B Nibble Code 100BASE-TX Transmit Blocks2 100BASE-TX Scrambler and MLT-3 Encoder InvalidNRZ to MLT-3 Encoding Diagram 3 100BASE-TX Transmit FramingVendor Model/Type 100BASE-TX Receive BlocksTransmit Driver 100BASE-TX Collision Detection Link Integrity 100BASE-TX Link Integrity and Auto-Negotiation SolutionCombination Tx/T4 Auto-Negotiation Solution Auto-NegotiationAdapter Mode Addresses Auto 10/100 Mbps Speed SelectionNetworking Silicon Datasheet 10BASE-T Transmit Blocks 10BASE-T Functionality in Adapter Mode10BASE-T Transmit Clock Generation 10BASE-T Receive Blocks10BASE-T Link Integrity 3 10BASE-T Error Detection and Reporting10BASE-T Collision Detection 10BASE-T Jabber Control Function10BASE-T Full Duplex Networking Silicon Datasheet Connectivity Repeater ModeSpecial Repeater Features Clock Signal Example Management Data Interface MDI Frame StructureMDI Registers 0 Bits Name Description DefaultMDI Registers TransitionRegister 1 Status Register Bit Definitions 10BASE-TRegister 2 82555 Identifier Register Bit Definitions MDI Registers 8 MDI Registers 16Register 17 82555 Special Control Bit Definitions 100BASE-TX150 Register 22 Receive Symbol Error Counter Bit Definitions Actled LiledDescription Bit Setting TechnologyAuto-Negotiation Functionality Priority TechnologyParallel Detect and Auto-Negotiation PriorityAuto-Negotiation and Parallel Detect Networking Silicon Datasheet LED Descriptions Networking Silicon Datasheet Loopback Reset and Miscellaneous Test ModesReset Scrambler BypassTest Instruction Coding Number Code Test Instruction Select Input to ToutAbsolute Maximum Ratings Electrical Specifications and Timing ParametersDC Characteristics General Operating Conditions11.3.3 100BASE-TX Voltage/Current DC Characteristics Total supply current 230 Leakage on analog pinsSymbol Parameter Conditions Min Typ Max Units AC CharacteristicsMII Clock Specifications MII Timing Parameters MII Clocks AC TimingRepeater Mode Timing Parameters RXC tri-stated aTransmit Packet Timing Parameters Squelch Test Timing ParametersJabber Timing Parameters Receive Packet Timing Parameters11.4.8 10BASE-T Normal Link Pulse NLP Timing Parameters Auto-Negotiation Fast Link Pulse FLP Timing ParametersReset Timing Parameters 11.4.11 X1 Clock Specifications11.4.12 100BASE-TX Transmitter AC Specification X1 Clock SpecificationsSymbol Description Min Norm Max 12.0 82555 Package Information10.0
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