Intel 82555 manual Reset Timing Parameters, 11.4.11 X1 Clock Specifications

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Networking Silicon — 82555

	Symbol	Parameter	Conditions	Min	Typ	Max	Units


T33	TFLP_BUR_NUM	Number of pulses in one burst		17		33
T34	TFLP_BUR_WID	FLP Burst width			2		ms
T35	TFLP_BUR_PER	FLP burst period		8		24	ms

T30

T31

T30

Fast Link Pulse

Clock Pulse

T35

Data Pulse

Clock Pulse

T34

FLP Bursts

Figure 24. Fast Link Pulse Timing Parameters

11.4.10Reset Timing Parameters

	Symbol	Parameter	Conditions	Min	Typ	Max	Units


T36	TRST_WID	Reset pulse width		500			ns
T37	TPUP_RST	Power-up to falling edge of reset		500			μs

Power Up (VCC)

RESET

T37

T36

Figure 25. Reset Timing Parameters

11.4.11X1 Clock Specifications

	Symbol	Parameter	Conditions	Min	Typ	Max	Units


T38	TX1_DC	X1 duty cycle		40		60	%
T39	TX1_PR	X1 period	±50 PPM		40		ns

Datasheet

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Contents 82555 10/100 Mbps LAN Physical Layer Interface Product FeaturesRevision Description Networking SiliconContents Repeater Mode Functional Overview IntroductionCompliance to Industry Standards Networking Silicon Architectural Overview 100 Mbps ModeMII TX Interface 10 Mbps ModeMedia Independent Interface MII Repeater mode only Transmit Error From RICYes Pin Numbers and Labels Pin DefinitionsPin Types Clock PinsTwisted Pair Ethernet TPE Pins Media Independent Interface MII PinsMedia Access Control/Repeater Interface Control Pins External Bias Pins LED PinsMiscellaneous Control Pins VCC Power and Ground PinsVSS 100BASE-TX Transmit Blocks 100BASE-TX Adapter Mode OperationSymbol 5B Symbol Code 4B Nibble Code 100BASE-TX Transmit Clock GenerationInvalid 2 100BASE-TX Scrambler and MLT-3 Encoder3 100BASE-TX Transmit Framing NRZ to MLT-3 Encoding DiagramTransmit Driver 100BASE-TX Receive BlocksVendor Model/Type 100BASE-TX Collision Detection Auto-Negotiation 100BASE-TX Link Integrity and Auto-Negotiation SolutionCombination Tx/T4 Auto-Negotiation Solution Link IntegrityAuto 10/100 Mbps Speed Selection Adapter Mode AddressesNetworking Silicon Datasheet 10BASE-T Receive Blocks 10BASE-T Functionality in Adapter Mode10BASE-T Transmit Clock Generation 10BASE-T Transmit Blocks10BASE-T Jabber Control Function 3 10BASE-T Error Detection and Reporting10BASE-T Collision Detection 10BASE-T Link Integrity10BASE-T Full Duplex Networking Silicon Datasheet Special Repeater Features Repeater ModeConnectivity Clock Signal Example MDI Frame Structure Management Data InterfaceTransition Bits Name Description DefaultMDI Registers MDI Registers 010BASE-T Register 1 Status Register Bit DefinitionsRegister 2 82555 Identifier Register Bit Definitions MDI Registers 16 MDI Registers 8100BASE-TX Register 17 82555 Special Control Bit Definitions150 Actled Liled Register 22 Receive Symbol Error Counter Bit DefinitionsPriority Technology Bit Setting TechnologyAuto-Negotiation Functionality DescriptionPriority Parallel Detect and Auto-NegotiationAuto-Negotiation and Parallel Detect Networking Silicon Datasheet LED Descriptions Networking Silicon Datasheet Scrambler Bypass Reset and Miscellaneous Test ModesReset LoopbackNumber Code Test Instruction Select Input to Tout Test Instruction CodingGeneral Operating Conditions Electrical Specifications and Timing ParametersDC Characteristics Absolute Maximum RatingsTotal supply current 230 Leakage on analog pins 11.3.3 100BASE-TX Voltage/Current DC CharacteristicsMII Clock Specifications AC CharacteristicsSymbol Parameter Conditions Min Typ Max Units MII Clocks AC Timing MII Timing ParametersRXC tri-stated a Repeater Mode Timing ParametersSquelch Test Timing Parameters Transmit Packet Timing ParametersReceive Packet Timing Parameters Jabber Timing ParametersAuto-Negotiation Fast Link Pulse FLP Timing Parameters 11.4.8 10BASE-T Normal Link Pulse NLP Timing Parameters11.4.11 X1 Clock Specifications Reset Timing ParametersX1 Clock Specifications 11.4.12 100BASE-TX Transmitter AC Specification12.0 82555 Package Information Symbol Description Min Norm Max10.0