Intel 82555 manual Power and Ground Pins, Vcc, Vss

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82555 — Networking Silicon

3.9Power and Ground Pins

Symbol	Pin		Type	Name and Function


VCC	7, 9, 15, 17, 19, 27, 29, 31, 36, 38, 40, 45, 58, 62,	I		Power: +5 V ± 5%
	64, 66, 73, 75, 83, 88, 93, 98

VSS	3, 8, 10, 14, 16, 18, 20, 26, 28, 30, 32, 35, 37, 39,	I		Ground: 0 V
	41, 46, 49, 53, 57, 61, 63, 65, 67, 72, 74, 78, 84, 89,
	91, 94, 99

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Datasheet

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Contents Product Features 82555 10/100 Mbps LAN Physical Layer InterfaceNetworking Silicon Revision DescriptionContents Repeater Mode Functional Overview IntroductionCompliance to Industry Standards Networking Silicon 100 Mbps Mode Architectural Overview10 Mbps Mode MII TX InterfaceMedia Independent Interface MII Repeater mode only Transmit Error From RICYes Pin Definitions Pin Numbers and LabelsClock Pins Twisted Pair Ethernet TPE PinsMedia Independent Interface MII Pins Pin TypesMedia Access Control/Repeater Interface Control Pins LED Pins External Bias PinsMiscellaneous Control Pins VCC Power and Ground PinsVSS 100BASE-TX Adapter Mode Operation Symbol 5B Symbol Code 4B Nibble Code100BASE-TX Transmit Clock Generation 100BASE-TX Transmit Blocks2 100BASE-TX Scrambler and MLT-3 Encoder InvalidNRZ to MLT-3 Encoding Diagram 3 100BASE-TX Transmit FramingTransmit Driver 100BASE-TX Receive BlocksVendor Model/Type 100BASE-TX Collision Detection 100BASE-TX Link Integrity and Auto-Negotiation Solution Combination Tx/T4 Auto-Negotiation SolutionLink Integrity Auto-NegotiationAdapter Mode Addresses Auto 10/100 Mbps Speed SelectionNetworking Silicon Datasheet 10BASE-T Functionality in Adapter Mode 10BASE-T Transmit Clock Generation10BASE-T Transmit Blocks 10BASE-T Receive Blocks3 10BASE-T Error Detection and Reporting 10BASE-T Collision Detection10BASE-T Link Integrity 10BASE-T Jabber Control Function10BASE-T Full Duplex Networking Silicon Datasheet Special Repeater Features Repeater ModeConnectivity Clock Signal Example Management Data Interface MDI Frame StructureBits Name Description Default MDI RegistersMDI Registers 0 TransitionRegister 1 Status Register Bit Definitions 10BASE-TRegister 2 82555 Identifier Register Bit Definitions MDI Registers 8 MDI Registers 16Register 17 82555 Special Control Bit Definitions 100BASE-TX150 Register 22 Receive Symbol Error Counter Bit Definitions Actled LiledBit Setting Technology Auto-Negotiation FunctionalityDescription Priority TechnologyParallel Detect and Auto-Negotiation PriorityAuto-Negotiation and Parallel Detect Networking Silicon Datasheet LED Descriptions Networking Silicon Datasheet Reset and Miscellaneous Test Modes ResetLoopback Scrambler BypassTest Instruction Coding Number Code Test Instruction Select Input to ToutElectrical Specifications and Timing Parameters DC CharacteristicsAbsolute Maximum Ratings General Operating Conditions11.3.3 100BASE-TX Voltage/Current DC Characteristics Total supply current 230 Leakage on analog pinsMII Clock Specifications AC CharacteristicsSymbol Parameter Conditions Min Typ Max Units MII Timing Parameters MII Clocks AC TimingRepeater Mode Timing Parameters RXC tri-stated aTransmit Packet Timing Parameters Squelch Test Timing ParametersJabber Timing Parameters Receive Packet Timing Parameters11.4.8 10BASE-T Normal Link Pulse NLP Timing Parameters Auto-Negotiation Fast Link Pulse FLP Timing ParametersReset Timing Parameters 11.4.11 X1 Clock Specifications11.4.12 100BASE-TX Transmitter AC Specification X1 Clock SpecificationsSymbol Description Min Norm Max 12.0 82555 Package Information10.0