Intel 82555 manual Networking Silicon, Revision Description

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82555 — Networking Silicon

■Low power consumption

—Typical total solution power including all resistors and magnetics:

-275 mA 100BASE-TX

-230 mA 10BASE-T

-250 mA Auto-Negotiation

—300 mA maximum total solution power in DTE (adapter) mode

—Power-down of 10BASE-T/100BASE- TX sections when not in use

Revision History

■Added modes for design, testing, and manufacturability

—Test Access Port (TAP)

-NAND Tree

-Board Level Functional Test (BIST)

—Programmable bypass for 4B/5B encoding/decoding and scrambler/ descrambler

—Diagnostic loopback mode

Revision

Revision

Description

Date

 

 

 

 

 

Jan. 1997

1.0

First external release of the preliminary datasheet

 

 

 

Apr. 1997

1.1

First release edition

 

 

 

Mar. 1998

2.0

General editing

 

 

 

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Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The 82555 10/100 Mbps LAN Physical Layer Interface may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:

Intel Corporation

P.O. Box 7641

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or call 1-800-879-4683.

Copyright © Intel Corporation, 1997

*Third-party brands and names are the property of their respective owners.

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Datasheet

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Contents Product Features 82555 10/100 Mbps LAN Physical Layer InterfaceNetworking Silicon Revision DescriptionContents Repeater Mode Compliance to Industry Standards IntroductionFunctional Overview Networking Silicon 100 Mbps Mode Architectural Overview10 Mbps Mode MII TX InterfaceMedia Independent Interface MII Yes Transmit Error From RICRepeater mode only Pin Definitions Pin Numbers and LabelsMedia Independent Interface MII Pins Clock PinsTwisted Pair Ethernet TPE Pins Pin TypesMedia Access Control/Repeater Interface Control Pins LED Pins External Bias PinsMiscellaneous Control Pins VSS Power and Ground PinsVCC 100BASE-TX Transmit Clock Generation 100BASE-TX Adapter Mode OperationSymbol 5B Symbol Code 4B Nibble Code 100BASE-TX Transmit Blocks2 100BASE-TX Scrambler and MLT-3 Encoder InvalidNRZ to MLT-3 Encoding Diagram 3 100BASE-TX Transmit FramingVendor Model/Type 100BASE-TX Receive BlocksTransmit Driver 100BASE-TX Collision Detection Link Integrity 100BASE-TX Link Integrity and Auto-Negotiation SolutionCombination Tx/T4 Auto-Negotiation Solution Auto-NegotiationAdapter Mode Addresses Auto 10/100 Mbps Speed SelectionNetworking Silicon Datasheet 10BASE-T Transmit Blocks 10BASE-T Functionality in Adapter Mode10BASE-T Transmit Clock Generation 10BASE-T Receive Blocks10BASE-T Link Integrity 3 10BASE-T Error Detection and Reporting10BASE-T Collision Detection 10BASE-T Jabber Control Function10BASE-T Full Duplex Networking Silicon Datasheet Connectivity Repeater ModeSpecial Repeater Features Clock Signal Example Management Data Interface MDI Frame StructureMDI Registers 0 Bits Name Description DefaultMDI Registers TransitionRegister 1 Status Register Bit Definitions 10BASE-TRegister 2 82555 Identifier Register Bit Definitions MDI Registers 8 MDI Registers 16Register 17 82555 Special Control Bit Definitions 100BASE-TX150 Register 22 Receive Symbol Error Counter Bit Definitions Actled LiledDescription Bit Setting TechnologyAuto-Negotiation Functionality Priority TechnologyParallel Detect and Auto-Negotiation PriorityAuto-Negotiation and Parallel Detect Networking Silicon Datasheet LED Descriptions Networking Silicon Datasheet Loopback Reset and Miscellaneous Test ModesReset Scrambler BypassTest Instruction Coding Number Code Test Instruction Select Input to ToutAbsolute Maximum Ratings Electrical Specifications and Timing ParametersDC Characteristics General Operating Conditions11.3.3 100BASE-TX Voltage/Current DC Characteristics Total supply current 230 Leakage on analog pinsSymbol Parameter Conditions Min Typ Max Units AC CharacteristicsMII Clock Specifications MII Timing Parameters MII Clocks AC TimingRepeater Mode Timing Parameters RXC tri-stated aTransmit Packet Timing Parameters Squelch Test Timing ParametersJabber Timing Parameters Receive Packet Timing Parameters11.4.8 10BASE-T Normal Link Pulse NLP Timing Parameters Auto-Negotiation Fast Link Pulse FLP Timing ParametersReset Timing Parameters 11.4.11 X1 Clock Specifications11.4.12 100BASE-TX Transmitter AC Specification X1 Clock SpecificationsSymbol Description Min Norm Max 12.0 82555 Package Information10.0
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