Intel 82555 manual 2 100BASE-TX Scrambler and MLT-3 Encoder, Invalid

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82555 — Networking Silicon

Table 2. 4B/5B Encoder

Symbol

5B Symbol Code

4B Nibble Code

 

 

 

E

11100

1110

 

 

 

F

11101

1111

 

 

 

I

11111

Inter Packet Idle Symbol

(No 4B)

 

 

 

 

 

J

11000

1st Start of Packet Symbol

0101

 

 

 

 

 

K

10001

2nd Start of Packet Symbol

0101

 

 

 

 

 

T

01101

1st End of Packet Symbol

 

 

 

R

00111

2nd End of Packet Symbol

and Flow Control

 

 

 

 

 

V

00000

INVALID

 

 

 

V

00001

INVALID

 

 

 

V

00010

INVALID

 

 

 

V

00011

INVALID

 

 

 

H

00100

INVALID

 

 

 

V

00101

INVALID

 

 

 

V

00110

INVALID

 

 

 

V

01000

INVALID

 

 

 

V

01100

INVALID

 

 

 

V

10000

Flow Control S

 

 

 

V

11001

INVALID

 

 

 

4.2.2100BASE-TX Scrambler and MLT-3 Encoder

Data is scrambled in 100BASE-TX in order to reduce electromagnetic emissions during long transmissions of high-frequency data codes. The scrambler logic accepts 5 bits from the 4B/5B encoder block and presents the scrambled data to the MLT-3 encoder. The 82555 implements the 11-bit stream cipher scrambler as adopted by the ANSI XT3T9.5 committee for UTP operation. The cipher equation used is:

X[n] = X[n-11] + X[n-9] (mod 2)

The MLT-3 encoder receives the scrambled Non-Return to Zero (NRZ) data stream from the scrambler and encodes the stream into MLT-3 for presentation to the driver. MLT-3 is similar to NRZI coding, but three levels are output instead of two. There are three output levels: positive, negative and zero. When an NRZ “0” arrives at the input of the encoder, the last output level is

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Datasheet

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Contents Product Features 82555 10/100 Mbps LAN Physical Layer InterfaceNetworking Silicon Revision DescriptionContents Repeater Mode Introduction Functional OverviewCompliance to Industry Standards Networking Silicon 100 Mbps Mode Architectural Overview10 Mbps Mode MII TX InterfaceMedia Independent Interface MII Transmit Error From RIC Repeater mode onlyYes Pin Definitions Pin Numbers and LabelsMedia Independent Interface MII Pins Clock PinsTwisted Pair Ethernet TPE Pins Pin TypesMedia Access Control/Repeater Interface Control Pins LED Pins External Bias PinsMiscellaneous Control Pins Power and Ground Pins VCCVSS 100BASE-TX Transmit Clock Generation 100BASE-TX Adapter Mode OperationSymbol 5B Symbol Code 4B Nibble Code 100BASE-TX Transmit Blocks2 100BASE-TX Scrambler and MLT-3 Encoder InvalidNRZ to MLT-3 Encoding Diagram 3 100BASE-TX Transmit Framing100BASE-TX Receive Blocks Transmit DriverVendor Model/Type 100BASE-TX Collision Detection Link Integrity 100BASE-TX Link Integrity and Auto-Negotiation SolutionCombination Tx/T4 Auto-Negotiation Solution Auto-NegotiationAdapter Mode Addresses Auto 10/100 Mbps Speed SelectionNetworking Silicon Datasheet 10BASE-T Transmit Blocks 10BASE-T Functionality in Adapter Mode10BASE-T Transmit Clock Generation 10BASE-T Receive Blocks10BASE-T Link Integrity 3 10BASE-T Error Detection and Reporting10BASE-T Collision Detection 10BASE-T Jabber Control Function10BASE-T Full Duplex Networking Silicon Datasheet Repeater Mode Special Repeater FeaturesConnectivity Clock Signal Example Management Data Interface MDI Frame StructureMDI Registers 0 Bits Name Description DefaultMDI Registers TransitionRegister 1 Status Register Bit Definitions 10BASE-TRegister 2 82555 Identifier Register Bit Definitions MDI Registers 8 MDI Registers 16Register 17 82555 Special Control Bit Definitions 100BASE-TX150 Register 22 Receive Symbol Error Counter Bit Definitions Actled LiledDescription Bit Setting TechnologyAuto-Negotiation Functionality Priority TechnologyParallel Detect and Auto-Negotiation PriorityAuto-Negotiation and Parallel Detect Networking Silicon Datasheet LED Descriptions Networking Silicon Datasheet Loopback Reset and Miscellaneous Test ModesReset Scrambler BypassTest Instruction Coding Number Code Test Instruction Select Input to ToutAbsolute Maximum Ratings Electrical Specifications and Timing ParametersDC Characteristics General Operating Conditions11.3.3 100BASE-TX Voltage/Current DC Characteristics Total supply current 230 Leakage on analog pinsAC Characteristics MII Clock SpecificationsSymbol Parameter Conditions Min Typ Max Units MII Timing Parameters MII Clocks AC TimingRepeater Mode Timing Parameters RXC tri-stated aTransmit Packet Timing Parameters Squelch Test Timing ParametersJabber Timing Parameters Receive Packet Timing Parameters11.4.8 10BASE-T Normal Link Pulse NLP Timing Parameters Auto-Negotiation Fast Link Pulse FLP Timing ParametersReset Timing Parameters 11.4.11 X1 Clock Specifications11.4.12 100BASE-TX Transmitter AC Specification X1 Clock SpecificationsSymbol Description Min Norm Max 12.0 82555 Package Information10.0