Intel manual Register 17 82555 Special Control Bit Definitions, 100BASE-TX

Page 36

82555 — Networking Silicon

7.2.3.1Register 16: 82555 Status and Control Register Bit Definitions

Bit(s)

Name

 

Description

Default

R/W

 

 

 

 

 

 

 

 

 

 

15

Flow Control

This bit enables PHY Base (Bay Technologies) flow

0

RW

 

 

control.

 

 

 

 

1

= Enable PHY Base flow control

 

 

 

 

0

= Disable PHY Base flow control

 

 

 

 

 

 

 

14

Reserved

These bits are reserved and should be set to 0b

0

RW

 

 

 

 

 

13

Carrier Sense

This bit enables the disconnect function.

0 (DTE

RW

 

Disconnect

1

= Disconnect function enabled (default in DTE)

1 (Rptr)

 

 

Control

 

 

0

= Disconnect function disabled (default in repeater)

 

 

 

 

 

 

 

 

 

 

 

12

Transmit Flow

This bit enables Transmit Flow Control

0

RW

 

Control Disable

1

= Transmit Flow Control enabled

 

 

 

 

 

 

 

 

0

= Transmit Flow Control disabled

 

 

 

 

 

 

 

11

Receive De-

This bit indicates status of the 100BASE-TX Receive

--

RO

 

Serializer In-Sync

De-Serializer In-Sync.

 

 

 

Indication

 

 

 

 

 

 

 

 

 

10

100BASE-TX

This bit indicates the power state of 100BASE-TX

--

RO

 

Power-Down

82555.

 

 

 

 

1

= Power-down

 

 

 

 

0

= Normal operation

 

 

 

 

 

 

 

9

10BASE-T

This bit indicates the power state of 10BASE-TX

--

RO

 

Power-Down

82555.

 

 

 

 

1

= Power-Down

 

 

 

 

0

= Normal operation

 

 

 

 

 

 

 

8

Polarity

This bit indicates 10BASE-T polarity.

--

RO

 

 

1

= Reverse polarity

 

 

 

 

0

= Normal polarity

 

 

 

 

 

 

 

7:3

Reserved

These bits are reserved and should be set to a

00000

RO

 

 

constant 0.

 

 

 

 

 

 

 

2

T4

This bit indicates the Auto-Negotiation result.

--

RO

 

 

1

= 100BASE-T4

 

 

 

 

0

= No 100BASE-T4

 

 

 

 

 

 

 

1

Speed

This bit indicates the Auto-Negotiation result.

--

RO

 

 

1

= 100 Mbps

 

 

 

 

0

= 10 Mbps

 

 

 

 

 

 

 

0

Duplex Mode

This bit indicates the Auto-Negotiation result.

--

RO

 

 

1

= Full Duplex

 

 

 

 

0

= Half Duplex

 

 

 

 

 

 

 

 

7.2.3.2Register 17: 82555 Special Control Bit Definitions

Bit(s)

Name

 

Description

Default

R/W

 

 

 

 

 

 

 

 

 

 

 

 

15

Scrambler By-

1

= By-pass Scrambler

0

RW

 

pass

0

= Normal operations

 

 

 

 

 

 

 

 

 

 

 

14

By-pass 4B/5B

1 = 4 bit to 5 bit by-pass

0

RW

 

 

0

= Normal operation

 

 

 

 

 

 

 

 

32

Datasheet

Page 35 Page 37
Image 36
Page 35 Page 37
Contents Product Features 82555 10/100 Mbps LAN Physical Layer InterfaceNetworking Silicon Revision DescriptionContents Repeater Mode Introduction Functional OverviewCompliance to Industry Standards Networking Silicon 100 Mbps Mode Architectural Overview10 Mbps Mode MII TX InterfaceMedia Independent Interface MII Transmit Error From RIC Repeater mode onlyYes Pin Definitions Pin Numbers and LabelsClock Pins Twisted Pair Ethernet TPE PinsMedia Independent Interface MII Pins Pin TypesMedia Access Control/Repeater Interface Control Pins LED Pins External Bias PinsMiscellaneous Control Pins Power and Ground Pins VCCVSS 100BASE-TX Adapter Mode Operation Symbol 5B Symbol Code 4B Nibble Code100BASE-TX Transmit Clock Generation 100BASE-TX Transmit Blocks2 100BASE-TX Scrambler and MLT-3 Encoder InvalidNRZ to MLT-3 Encoding Diagram 3 100BASE-TX Transmit Framing100BASE-TX Receive Blocks Transmit DriverVendor Model/Type 100BASE-TX Collision Detection 100BASE-TX Link Integrity and Auto-Negotiation Solution Combination Tx/T4 Auto-Negotiation SolutionLink Integrity Auto-NegotiationAdapter Mode Addresses Auto 10/100 Mbps Speed SelectionNetworking Silicon Datasheet 10BASE-T Functionality in Adapter Mode 10BASE-T Transmit Clock Generation10BASE-T Transmit Blocks 10BASE-T Receive Blocks3 10BASE-T Error Detection and Reporting 10BASE-T Collision Detection10BASE-T Link Integrity 10BASE-T Jabber Control Function10BASE-T Full Duplex Networking Silicon Datasheet Repeater Mode Special Repeater FeaturesConnectivity Clock Signal Example Management Data Interface MDI Frame StructureBits Name Description Default MDI RegistersMDI Registers 0 Transition Register 1 Status Register Bit Definitions 10BASE-TRegister 2 82555 Identifier Register Bit Definitions MDI Registers 8 MDI Registers 16Register 17 82555 Special Control Bit Definitions 100BASE-TX150 Register 22 Receive Symbol Error Counter Bit Definitions Actled LiledBit Setting Technology Auto-Negotiation FunctionalityDescription Priority TechnologyParallel Detect and Auto-Negotiation PriorityAuto-Negotiation and Parallel Detect Networking Silicon Datasheet LED Descriptions Networking Silicon Datasheet Reset and Miscellaneous Test Modes ResetLoopback Scrambler BypassTest Instruction Coding Number Code Test Instruction Select Input to ToutElectrical Specifications and Timing Parameters DC CharacteristicsAbsolute Maximum Ratings General Operating Conditions11.3.3 100BASE-TX Voltage/Current DC Characteristics Total supply current 230 Leakage on analog pinsAC Characteristics MII Clock SpecificationsSymbol Parameter Conditions Min Typ Max Units MII Timing Parameters MII Clocks AC TimingRepeater Mode Timing Parameters RXC tri-stated aTransmit Packet Timing Parameters Squelch Test Timing ParametersJabber Timing Parameters Receive Packet Timing Parameters11.4.8 10BASE-T Normal Link Pulse NLP Timing Parameters Auto-Negotiation Fast Link Pulse FLP Timing ParametersReset Timing Parameters 11.4.11 X1 Clock Specifications11.4.12 100BASE-TX Transmitter AC Specification X1 Clock SpecificationsSymbol Description Min Norm Max 12.0 82555 Package Information10.0
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