Intel 82555 manual 100BASE-TX Collision Detection

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Networking Silicon — 82555

4.3.1Adaptive Equalizer

The distorted MLT-3 signal at the end of the wire is restored by the equalizer. The equalizer performs adaptation based on the shape of the received signal, equalizing the signal to meet superior Data Dependent Jitter performance.

4.3.2Receive Clock and Data Recovery

The clock recovery circuit uses advanced digital signal processing technology to compensate for various signal jitter causes. The circuit recovers the 125 MHz clock and data and presents the data to the MLT-3 decoder.

4.3.3MLT-3 Decoder, Descrambler, and Receive Digital Section

The 82555 first decodes the MLT-3 data; afterwards, the descrambler reproduces the 5B symbols originated in the transmitter. The descrambling is based on synchronization to the transmit 11-bit Linear Feedback Shift Register (LFSR) during idle. The data is decoded at the 4B/5B decoder.

Once the 4B symbols are obtained, the 82555 outputs the receive data to the CSMA unit.

4.3.4100BASE-TX Receive Framing

The 82555 does not differentiate between the fields of the MAC frame containing preamble, start of frame delimiter, data and CRC. During 100 Mbps reception, the 82555 differentiates between the idle condition ("L" symbols on the wire) and the preamble or start of frame delimiter. When two non-consecutive bits are 0b within 10 bits (125 Mbps 5B data coding) the 82555 immediately asserts the CRS signal. When the “JK” symbols (“11000, 10001”) are fully recognized, the 82555 asserts the RXDV signal and provides the data received on the MII RXD[3:0] to the Receive Clock. If the “JK” symbol is not recognized (“false carrier sense”), the CRS signal is immediately de- asserted and RXERR is asserted. Otherwise, the valid data is passed through the MII until the 82555 finds the “TR” (“01101, 00111”) and idle symbols in order to de-assert TXDV and CRS.

4.3.5100BASE-TX Receive Error Detection and Reporting

In 100BASE-TX mode, the 82555 can detect errors in receive data in a number of ways. Any of the following conditions is considered an error:

•Link integrity fails in the middle of frame reception.

•The start of stream delimiter “JK” symbol is not fully detected after idle.

•An invalid symbol is detected at the 4B/5B decoder.

•Idle is detected in the middle of a frame (before “TR” is detected).

When any of the above error conditions occurs, the 82555 immediately asserts the Receive Error signal to the MAC. The RXERR signal is asserted as long as the receive error condition persists on the receive pair.

4.4100BASE-TX Collision Detection

100BASE-TX collisions in half duplex mode only are detected similarly to 10BASE-T collision detection, via simultaneous transmission and reception.

Datasheet

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Contents 82555 10/100 Mbps LAN Physical Layer Interface Product FeaturesRevision Description Networking SiliconContents Repeater Mode Introduction Functional OverviewCompliance to Industry Standards Networking Silicon Architectural Overview 100 Mbps ModeMII TX Interface 10 Mbps ModeMedia Independent Interface MII Transmit Error From RIC Repeater mode onlyYes Pin Numbers and Labels Pin DefinitionsTwisted Pair Ethernet TPE Pins Clock PinsMedia Independent Interface MII Pins Pin TypesMedia Access Control/Repeater Interface Control Pins External Bias Pins LED PinsMiscellaneous Control Pins Power and Ground Pins VCCVSS Symbol 5B Symbol Code 4B Nibble Code 100BASE-TX Adapter Mode Operation100BASE-TX Transmit Clock Generation 100BASE-TX Transmit BlocksInvalid 2 100BASE-TX Scrambler and MLT-3 Encoder3 100BASE-TX Transmit Framing NRZ to MLT-3 Encoding Diagram100BASE-TX Receive Blocks Transmit DriverVendor Model/Type 100BASE-TX Collision Detection Combination Tx/T4 Auto-Negotiation Solution 100BASE-TX Link Integrity and Auto-Negotiation SolutionLink Integrity Auto-NegotiationAuto 10/100 Mbps Speed Selection Adapter Mode AddressesNetworking Silicon Datasheet 10BASE-T Transmit Clock Generation 10BASE-T Functionality in Adapter Mode10BASE-T Transmit Blocks 10BASE-T Receive Blocks10BASE-T Collision Detection 3 10BASE-T Error Detection and Reporting10BASE-T Link Integrity 10BASE-T Jabber Control Function10BASE-T Full Duplex Networking Silicon Datasheet Repeater Mode Special Repeater FeaturesConnectivity Clock Signal Example MDI Frame Structure Management Data InterfaceMDI Registers Bits Name Description DefaultMDI Registers 0 Transition10BASE-T Register 1 Status Register Bit DefinitionsRegister 2 82555 Identifier Register Bit Definitions MDI Registers 16 MDI Registers 8100BASE-TX Register 17 82555 Special Control Bit Definitions150 Actled Liled Register 22 Receive Symbol Error Counter Bit DefinitionsAuto-Negotiation Functionality Bit Setting TechnologyDescription Priority TechnologyPriority Parallel Detect and Auto-NegotiationAuto-Negotiation and Parallel Detect Networking Silicon Datasheet LED Descriptions Networking Silicon Datasheet Reset Reset and Miscellaneous Test ModesLoopback Scrambler BypassNumber Code Test Instruction Select Input to Tout Test Instruction CodingDC Characteristics Electrical Specifications and Timing ParametersAbsolute Maximum Ratings General Operating ConditionsTotal supply current 230 Leakage on analog pins 11.3.3 100BASE-TX Voltage/Current DC CharacteristicsAC Characteristics MII Clock SpecificationsSymbol Parameter Conditions Min Typ Max Units MII Clocks AC Timing MII Timing ParametersRXC tri-stated a Repeater Mode Timing ParametersSquelch Test Timing Parameters Transmit Packet Timing ParametersReceive Packet Timing Parameters Jabber Timing ParametersAuto-Negotiation Fast Link Pulse FLP Timing Parameters 11.4.8 10BASE-T Normal Link Pulse NLP Timing Parameters11.4.11 X1 Clock Specifications Reset Timing ParametersX1 Clock Specifications 11.4.12 100BASE-TX Transmitter AC Specification12.0 82555 Package Information Symbol Description Min Norm Max10.0
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