Intel
82555
manual
Networking Silicon Datasheet
Specs
DC Characteristics
NRZ to MLT-3 Encoding Diagram
Networking Silicon Datasheet
Clock Signal Example
Transmit Error From RIC
Reset
Clock Pins
Bit Setting Technology
Power and Ground Pins
Page 28
82555 — Networking Silicon
24
Datasheet
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Page 27
Page 29
Contents
Product Features
82555 10/100 Mbps LAN Physical Layer Interface
Networking Silicon
Revision Description
Contents
Repeater Mode
Functional Overview
Introduction
Compliance to Industry Standards
Networking Silicon
100 Mbps Mode
Architectural Overview
10 Mbps Mode
MII TX Interface
Media Independent Interface MII
Repeater mode only
Transmit Error From RIC
Yes
Pin Definitions
Pin Numbers and Labels
Clock Pins
Twisted Pair Ethernet TPE Pins
Media Independent Interface MII Pins
Pin Types
Media Access Control/Repeater Interface Control Pins
LED Pins
External Bias Pins
Miscellaneous Control Pins
VCC
Power and Ground Pins
VSS
100BASE-TX Adapter Mode Operation
Symbol 5B Symbol Code 4B Nibble Code
100BASE-TX Transmit Clock Generation
100BASE-TX Transmit Blocks
2 100BASE-TX Scrambler and MLT-3 Encoder
Invalid
NRZ to MLT-3 Encoding Diagram
3 100BASE-TX Transmit Framing
Transmit Driver
100BASE-TX Receive Blocks
Vendor Model/Type
100BASE-TX Collision Detection
100BASE-TX Link Integrity and Auto-Negotiation Solution
Combination Tx/T4 Auto-Negotiation Solution
Link Integrity
Auto-Negotiation
Adapter Mode Addresses
Auto 10/100 Mbps Speed Selection
Networking Silicon Datasheet
10BASE-T Functionality in Adapter Mode
10BASE-T Transmit Clock Generation
10BASE-T Transmit Blocks
10BASE-T Receive Blocks
3 10BASE-T Error Detection and Reporting
10BASE-T Collision Detection
10BASE-T Link Integrity
10BASE-T Jabber Control Function
10BASE-T Full Duplex
Networking Silicon Datasheet
Special Repeater Features
Repeater Mode
Connectivity
Clock Signal Example
Management Data Interface
MDI Frame Structure
Bits Name Description Default
MDI Registers
MDI Registers 0
Transition
Register 1 Status Register Bit Definitions
10BASE-T
Register 2 82555 Identifier Register Bit Definitions
MDI Registers 8
MDI Registers 16
Register 17 82555 Special Control Bit Definitions
100BASE-TX
150
Register 22 Receive Symbol Error Counter Bit Definitions
Actled Liled
Bit Setting Technology
Auto-Negotiation Functionality
Description
Priority Technology
Parallel Detect and Auto-Negotiation
Priority
Auto-Negotiation and Parallel Detect
Networking Silicon Datasheet
LED Descriptions
Networking Silicon Datasheet
Reset and Miscellaneous Test Modes
Reset
Loopback
Scrambler Bypass
Test Instruction Coding
Number Code Test Instruction Select Input to Tout
Electrical Specifications and Timing Parameters
DC Characteristics
Absolute Maximum Ratings
General Operating Conditions
11.3.3 100BASE-TX Voltage/Current DC Characteristics
Total supply current 230 Leakage on analog pins
MII Clock Specifications
AC Characteristics
Symbol Parameter Conditions Min Typ Max Units
MII Timing Parameters
MII Clocks AC Timing
Repeater Mode Timing Parameters
RXC tri-stated a
Transmit Packet Timing Parameters
Squelch Test Timing Parameters
Jabber Timing Parameters
Receive Packet Timing Parameters
11.4.8 10BASE-T Normal Link Pulse NLP Timing Parameters
Auto-Negotiation Fast Link Pulse FLP Timing Parameters
Reset Timing Parameters
11.4.11 X1 Clock Specifications
11.4.12 100BASE-TX Transmitter AC Specification
X1 Clock Specifications
Symbol Description Min Norm Max
12.0 82555 Package Information
10.0
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