Intel 82555 manual Networking Silicon

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82555 — Networking Silicon

The 82555 also complies with the IEEE 802.3u Auto-Negotiation and the IEEE 802.3x Full Duplex Flow Control sections. The MAC interface on the 82555 is a superset of the IEEE 802.3u Media Independent Interface (MII) standard.

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Datasheet

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Contents Product Features 82555 10/100 Mbps LAN Physical Layer InterfaceNetworking Silicon Revision DescriptionContents Repeater Mode Introduction Functional OverviewCompliance to Industry Standards Networking Silicon 100 Mbps Mode Architectural Overview10 Mbps Mode MII TX InterfaceMedia Independent Interface MII Transmit Error From RIC Repeater mode onlyYes Pin Definitions Pin Numbers and LabelsMedia Independent Interface MII Pins Clock PinsTwisted Pair Ethernet TPE Pins Pin TypesMedia Access Control/Repeater Interface Control Pins LED Pins External Bias PinsMiscellaneous Control Pins Power and Ground Pins VCCVSS 100BASE-TX Transmit Clock Generation 100BASE-TX Adapter Mode OperationSymbol 5B Symbol Code 4B Nibble Code 100BASE-TX Transmit Blocks2 100BASE-TX Scrambler and MLT-3 Encoder InvalidNRZ to MLT-3 Encoding Diagram 3 100BASE-TX Transmit Framing100BASE-TX Receive Blocks Transmit DriverVendor Model/Type 100BASE-TX Collision Detection Link Integrity 100BASE-TX Link Integrity and Auto-Negotiation SolutionCombination Tx/T4 Auto-Negotiation Solution Auto-NegotiationAdapter Mode Addresses Auto 10/100 Mbps Speed SelectionNetworking Silicon Datasheet 10BASE-T Transmit Blocks 10BASE-T Functionality in Adapter Mode10BASE-T Transmit Clock Generation 10BASE-T Receive Blocks10BASE-T Link Integrity 3 10BASE-T Error Detection and Reporting10BASE-T Collision Detection 10BASE-T Jabber Control Function10BASE-T Full Duplex Networking Silicon Datasheet Repeater Mode Special Repeater FeaturesConnectivity Clock Signal Example Management Data Interface MDI Frame StructureMDI Registers 0 Bits Name Description DefaultMDI Registers TransitionRegister 1 Status Register Bit Definitions 10BASE-TRegister 2 82555 Identifier Register Bit Definitions MDI Registers 8 MDI Registers 16Register 17 82555 Special Control Bit Definitions 100BASE-TX150 Register 22 Receive Symbol Error Counter Bit Definitions Actled LiledDescription Bit Setting TechnologyAuto-Negotiation Functionality Priority TechnologyParallel Detect and Auto-Negotiation PriorityAuto-Negotiation and Parallel Detect Networking Silicon Datasheet LED Descriptions Networking Silicon Datasheet Loopback Reset and Miscellaneous Test ModesReset Scrambler BypassTest Instruction Coding Number Code Test Instruction Select Input to ToutAbsolute Maximum Ratings Electrical Specifications and Timing ParametersDC Characteristics General Operating Conditions11.3.3 100BASE-TX Voltage/Current DC Characteristics Total supply current 230 Leakage on analog pinsAC Characteristics MII Clock SpecificationsSymbol Parameter Conditions Min Typ Max Units MII Timing Parameters MII Clocks AC TimingRepeater Mode Timing Parameters RXC tri-stated aTransmit Packet Timing Parameters Squelch Test Timing ParametersJabber Timing Parameters Receive Packet Timing Parameters11.4.8 10BASE-T Normal Link Pulse NLP Timing Parameters Auto-Negotiation Fast Link Pulse FLP Timing ParametersReset Timing Parameters 11.4.11 X1 Clock Specifications11.4.12 100BASE-TX Transmitter AC Specification X1 Clock SpecificationsSymbol Description Min Norm Max 12.0 82555 Package Information10.0