Intel 82555 manual Pin Definitions, Pin Numbers and Labels

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Networking Silicon — 82555

3.0Pin Definitions

All active digital pins are defined to have transistor-to-transistor logic voltage levels except the X1 and X2 crystal signals. The transmit differential and receive differential pins are specified as analog outputs and inputs, respectively.

The figure below show the pin locations on the 82555 component. The following subsections describe the pin functions.

Figure 5. 82555 Pin Numbers and Labels

Datasheet

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Contents 82555 10/100 Mbps LAN Physical Layer Interface Product FeaturesRevision Description Networking SiliconContents Repeater Mode Compliance to Industry Standards IntroductionFunctional Overview Networking Silicon Architectural Overview 100 Mbps ModeMII TX Interface 10 Mbps ModeMedia Independent Interface MII Yes Transmit Error From RICRepeater mode only Pin Numbers and Labels Pin DefinitionsPin Types Clock PinsTwisted Pair Ethernet TPE Pins Media Independent Interface MII PinsMedia Access Control/Repeater Interface Control Pins External Bias Pins LED PinsMiscellaneous Control Pins VSS Power and Ground PinsVCC 100BASE-TX Transmit Blocks 100BASE-TX Adapter Mode OperationSymbol 5B Symbol Code 4B Nibble Code 100BASE-TX Transmit Clock GenerationInvalid 2 100BASE-TX Scrambler and MLT-3 Encoder3 100BASE-TX Transmit Framing NRZ to MLT-3 Encoding DiagramVendor Model/Type 100BASE-TX Receive BlocksTransmit Driver 100BASE-TX Collision Detection Auto-Negotiation 100BASE-TX Link Integrity and Auto-Negotiation SolutionCombination Tx/T4 Auto-Negotiation Solution Link IntegrityAuto 10/100 Mbps Speed Selection Adapter Mode AddressesNetworking Silicon Datasheet 10BASE-T Receive Blocks 10BASE-T Functionality in Adapter Mode10BASE-T Transmit Clock Generation 10BASE-T Transmit Blocks10BASE-T Jabber Control Function 3 10BASE-T Error Detection and Reporting10BASE-T Collision Detection 10BASE-T Link Integrity10BASE-T Full Duplex Networking Silicon Datasheet Connectivity Repeater ModeSpecial Repeater Features Clock Signal Example MDI Frame Structure Management Data InterfaceTransition Bits Name Description DefaultMDI Registers MDI Registers 010BASE-T Register 1 Status Register Bit DefinitionsRegister 2 82555 Identifier Register Bit Definitions MDI Registers 16 MDI Registers 8100BASE-TX Register 17 82555 Special Control Bit Definitions150 Actled Liled Register 22 Receive Symbol Error Counter Bit DefinitionsPriority Technology Bit Setting TechnologyAuto-Negotiation Functionality DescriptionPriority Parallel Detect and Auto-NegotiationAuto-Negotiation and Parallel Detect Networking Silicon Datasheet LED Descriptions Networking Silicon Datasheet Scrambler Bypass Reset and Miscellaneous Test ModesReset LoopbackNumber Code Test Instruction Select Input to Tout Test Instruction CodingGeneral Operating Conditions Electrical Specifications and Timing ParametersDC Characteristics Absolute Maximum RatingsTotal supply current 230 Leakage on analog pins 11.3.3 100BASE-TX Voltage/Current DC CharacteristicsSymbol Parameter Conditions Min Typ Max Units AC CharacteristicsMII Clock Specifications MII Clocks AC Timing MII Timing ParametersRXC tri-stated a Repeater Mode Timing ParametersSquelch Test Timing Parameters Transmit Packet Timing ParametersReceive Packet Timing Parameters Jabber Timing ParametersAuto-Negotiation Fast Link Pulse FLP Timing Parameters 11.4.8 10BASE-T Normal Link Pulse NLP Timing Parameters11.4.11 X1 Clock Specifications Reset Timing ParametersX1 Clock Specifications 11.4.12 100BASE-TX Transmitter AC Specification12.0 82555 Package Information Symbol Description Min Norm Max10.0