Intel 82555 manual Repeater Mode, Special Repeater Features, Connectivity

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Networking Silicon — 82555

6.0Repeater Mode

The 82555 has a compete set of repeater features making it the ideal PHY for Class 1 (MII) repeater designs. The 82555 works in repeater mode when the RPT signal (pin 50) is high. The FRC100 signal (pin 51) determines which type of repeater is supported, either 100BASE-TX or 10BASE-T.

6.1Special Repeater Features

Special features of the 82555 repeater mode operation include:

•Fully IEEE compliant with automatic carrier disconnect.

The 82555 will disconnect when it receives false carrier detects. Either a long series of valid idle symbols or a valid “JK” pair will cause it to reconnect.

•Narrow 14 mm analog side that enables tight packing of multiple PHYs, which is ideal for 8, 12, 18, 24, or even 32 port repeater designs.

•Very low emissions and high noise immunity.

•32 configurable addresses through five address lines.

•Auto-Negotiation disable function.

In repeater mode, the Auto-Negotiation function is not used for configuration purposes. When Auto-Negotiation is enabled in repeater mode, the MII management will be able to obtain data from the MDI Auto-Negotiation register about the remote partner. This is a feature for hub management allowing a 10/100 Mbps repeater design to automatically detect whether or not it can operate at 100 Mbps. If the ANDIS signal is de-asserted, the Auto-Negotiation feature will be disabled.

•Forced 10 Mbps or 100 Mbps operation (allows for a 10/100 repeater design).

•Receive port enable function.

The PORTEN signal is a glueless interface to the Repeater Interface Controller (RIC). When the PORTEN signal is low, all receive signals are tri-stated, except CRS and COL.

•26-bit PHY budget for round trip.

The total PHY bit budget is 8 bits from the MII to the wire and 18 bits from the wire to the MII.

•Static 2.5 MHz (10BASE-T) or 25 MHz (100BASE-TX) clock input for repeater designs (issued by RIC).

The 82555 clock source is fixed between Resets. There is one input, either 2.5 MHz or 25 MHz, as indicated by the level at the FRC100 pin. All clocks have a common source generation so the that PPM is 0 between them (X1, 2.5 MHz and 25 MHz).

•DTE (adapter) features not available in repeater mode: full duplex, flow control, and the combination Auto-Negotiation interface for T4.

6.2Connectivity

A 25 MHz buffered oscillator can provide the clock to all of the 82555 devices. A 2.5 MHz (10 Mbps) or a 25 MHz (100 Mbps) signal is required to clock the RIC and the TXC signal in the PHYs. TXD[3:0], TXERR, RXC, RXD[3:0], RXDV, and RXERR are single-bus (shortened) for all

Datasheet

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Contents 82555 10/100 Mbps LAN Physical Layer Interface Product FeaturesRevision Description Networking SiliconContents Repeater Mode Compliance to Industry Standards IntroductionFunctional Overview Networking Silicon Architectural Overview 100 Mbps ModeMII TX Interface 10 Mbps ModeMedia Independent Interface MII Yes Transmit Error From RICRepeater mode only Pin Numbers and Labels Pin DefinitionsTwisted Pair Ethernet TPE Pins Clock PinsMedia Independent Interface MII Pins Pin TypesMedia Access Control/Repeater Interface Control Pins External Bias Pins LED PinsMiscellaneous Control Pins VSS Power and Ground PinsVCC Symbol 5B Symbol Code 4B Nibble Code 100BASE-TX Adapter Mode Operation100BASE-TX Transmit Clock Generation 100BASE-TX Transmit BlocksInvalid 2 100BASE-TX Scrambler and MLT-3 Encoder3 100BASE-TX Transmit Framing NRZ to MLT-3 Encoding DiagramVendor Model/Type 100BASE-TX Receive BlocksTransmit Driver 100BASE-TX Collision Detection Combination Tx/T4 Auto-Negotiation Solution 100BASE-TX Link Integrity and Auto-Negotiation SolutionLink Integrity Auto-NegotiationAuto 10/100 Mbps Speed Selection Adapter Mode AddressesNetworking Silicon Datasheet 10BASE-T Transmit Clock Generation 10BASE-T Functionality in Adapter Mode10BASE-T Transmit Blocks 10BASE-T Receive Blocks10BASE-T Collision Detection 3 10BASE-T Error Detection and Reporting10BASE-T Link Integrity 10BASE-T Jabber Control Function10BASE-T Full Duplex Networking Silicon Datasheet Connectivity Repeater ModeSpecial Repeater Features Clock Signal Example MDI Frame Structure Management Data InterfaceMDI Registers Bits Name Description DefaultMDI Registers 0 Transition10BASE-T Register 1 Status Register Bit DefinitionsRegister 2 82555 Identifier Register Bit Definitions MDI Registers 16 MDI Registers 8100BASE-TX Register 17 82555 Special Control Bit Definitions150 Actled Liled Register 22 Receive Symbol Error Counter Bit DefinitionsAuto-Negotiation Functionality Bit Setting TechnologyDescription Priority TechnologyPriority Parallel Detect and Auto-NegotiationAuto-Negotiation and Parallel Detect Networking Silicon Datasheet LED Descriptions Networking Silicon Datasheet Reset Reset and Miscellaneous Test ModesLoopback Scrambler BypassNumber Code Test Instruction Select Input to Tout Test Instruction CodingDC Characteristics Electrical Specifications and Timing ParametersAbsolute Maximum Ratings General Operating ConditionsTotal supply current 230 Leakage on analog pins 11.3.3 100BASE-TX Voltage/Current DC CharacteristicsSymbol Parameter Conditions Min Typ Max Units AC CharacteristicsMII Clock Specifications MII Clocks AC Timing MII Timing ParametersRXC tri-stated a Repeater Mode Timing ParametersSquelch Test Timing Parameters Transmit Packet Timing ParametersReceive Packet Timing Parameters Jabber Timing ParametersAuto-Negotiation Fast Link Pulse FLP Timing Parameters 11.4.8 10BASE-T Normal Link Pulse NLP Timing Parameters11.4.11 X1 Clock Specifications Reset Timing ParametersX1 Clock Specifications 11.4.12 100BASE-TX Transmitter AC Specification12.0 82555 Package Information Symbol Description Min Norm Max10.0
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