Intel 82555 manual 100BASE-TX Link Integrity and Auto-Negotiation Solution

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82555 — Networking Silicon

4.5100BASE-TX Link Integrity and Auto-Negotiation Solution

The 82555’s Auto-Negotiation function automatically configures the device to the technology, media, and speed to operate with its link partner. Auto-Negotiation is widely described in IEEE specification 802.3u, Clause 28. The 82555 supports 10BASE-T half duplex, 10BASE-T full duplex, 100BASE-TX half duplex, and 100BASE-TX full duplex.

The 82555 has two Physical Medium Attachment (PMA) technologies with its link integrity function, 10BASE-T and 100BASE-TX. The 82555 also has a special interface defined between itself and a PHY-T4 in order to implement an Auto-Negotiation combination card.

4.5.1Link Integrity

In 100BASE-TX, the link integrity function is determined by a stable signal status coming from the TP-PMD block. Signal status is asserted when the PMD detects breaking squelch energy and the right bit error rate according to the ANSI specification.

4.5.2Auto-Negotiation

The 82555 fully supports IEEE 802.3u, Clause 28. In DTE (adapter) mode, the technology, 10BASE-T or 100BASE-TX, is determined by the Auto-Negotiation result. In repeater mode only, this function can be disabled by pin configuration. If the T4ADV pin is active, the Auto- Negotiation function will advertise and negotiate T4 technology.

Speed and duplex auto-select are functions of Auto-Negotiation. However, these parameters may be manually configured via the MII management interface (MDI registers).

4.5.3Combination Tx/T4 Auto-Negotiation Solution

The Auto-Negotiation function is available in both the 82555 and a PHY-T4. For these PHYs to operate together, some arbitration at the PMA level is required and the Auto-Negotiation function of one of the PHYs must be disabled. For this purpose, the 82555 is defined as the master; and the PHY-T4, the slave. In combination mode, only the 82555’s Auto-Negotiation function is enabled (the PHY-T4’s Auto-Negotiation is disabled).

In a combination board, a PHY-T4 is used only to support 100BASE-T4 operation and the 82555 is sued to support 100BASE-TX full or half duplex and 10BASE-T full or half duplex as determined by the Auto-Negotiation or Parallel Detection function.

Combination mode is available only in DTE (adapter) mode with the following pin interface:

•T4ADV (pin 54): Enables T4 technology in a PHY-TX Auto-Negotiation system.

•SLVTRI (pin 52): Disables the PHY-T4.The PHY-T4 is enabled only if the T4 technology has been detected by Auto-Negotiation or Parallel Detection.

•LISTAT (pin 6): Indicates valid link on the PHY-T4. When SLVTRI is de-asserted, the PHY- T4 should be active.

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Datasheet

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Contents Product Features 82555 10/100 Mbps LAN Physical Layer InterfaceNetworking Silicon Revision DescriptionContents Repeater Mode Functional Overview IntroductionCompliance to Industry Standards Networking Silicon 100 Mbps Mode Architectural Overview10 Mbps Mode MII TX InterfaceMedia Independent Interface MII Repeater mode only Transmit Error From RICYes Pin Definitions Pin Numbers and LabelsMedia Independent Interface MII Pins Clock PinsTwisted Pair Ethernet TPE Pins Pin TypesMedia Access Control/Repeater Interface Control Pins LED Pins External Bias PinsMiscellaneous Control Pins VCC Power and Ground PinsVSS 100BASE-TX Transmit Clock Generation 100BASE-TX Adapter Mode OperationSymbol 5B Symbol Code 4B Nibble Code 100BASE-TX Transmit Blocks2 100BASE-TX Scrambler and MLT-3 Encoder InvalidNRZ to MLT-3 Encoding Diagram 3 100BASE-TX Transmit FramingTransmit Driver 100BASE-TX Receive BlocksVendor Model/Type 100BASE-TX Collision Detection Link Integrity 100BASE-TX Link Integrity and Auto-Negotiation SolutionCombination Tx/T4 Auto-Negotiation Solution Auto-NegotiationAdapter Mode Addresses Auto 10/100 Mbps Speed SelectionNetworking Silicon Datasheet 10BASE-T Transmit Blocks 10BASE-T Functionality in Adapter Mode10BASE-T Transmit Clock Generation 10BASE-T Receive Blocks10BASE-T Link Integrity 3 10BASE-T Error Detection and Reporting10BASE-T Collision Detection 10BASE-T Jabber Control Function10BASE-T Full Duplex Networking Silicon Datasheet Special Repeater Features Repeater ModeConnectivity Clock Signal Example Management Data Interface MDI Frame StructureMDI Registers 0 Bits Name Description DefaultMDI Registers TransitionRegister 1 Status Register Bit Definitions 10BASE-TRegister 2 82555 Identifier Register Bit Definitions MDI Registers 8 MDI Registers 16Register 17 82555 Special Control Bit Definitions 100BASE-TX150 Register 22 Receive Symbol Error Counter Bit Definitions Actled LiledDescription Bit Setting TechnologyAuto-Negotiation Functionality Priority TechnologyParallel Detect and Auto-Negotiation PriorityAuto-Negotiation and Parallel Detect Networking Silicon Datasheet LED Descriptions Networking Silicon Datasheet Loopback Reset and Miscellaneous Test ModesReset Scrambler BypassTest Instruction Coding Number Code Test Instruction Select Input to ToutAbsolute Maximum Ratings Electrical Specifications and Timing ParametersDC Characteristics General Operating Conditions11.3.3 100BASE-TX Voltage/Current DC Characteristics Total supply current 230 Leakage on analog pinsMII Clock Specifications AC CharacteristicsSymbol Parameter Conditions Min Typ Max Units MII Timing Parameters MII Clocks AC TimingRepeater Mode Timing Parameters RXC tri-stated aTransmit Packet Timing Parameters Squelch Test Timing ParametersJabber Timing Parameters Receive Packet Timing Parameters11.4.8 10BASE-T Normal Link Pulse NLP Timing Parameters Auto-Negotiation Fast Link Pulse FLP Timing ParametersReset Timing Parameters 11.4.11 X1 Clock Specifications11.4.12 100BASE-TX Transmitter AC Specification X1 Clock SpecificationsSymbol Description Min Norm Max 12.0 82555 Package Information10.0
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