Intel 82555 manual 150

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Networking Silicon — 82555

Bit(s)	Name		Description	Default	R/W


13	Force Transmit H-	1	= Force transmit H-pattern	0	RW
	Pattern	0	= Normal operation
		0	= Normal operation

12	Force 34 Transmit	1	= Force 34 transmit pattern	0	RW
	Pattern	0	= Normal operation
		0	= Normal operation

11	Good Link	1 = 100BASE-TX link good		0	RW
		0	= Normal operation

10	Reserved	This bit is reserved and should be set to 0b.		0	RW

9	Transmit Carrier	1	= Transmit Carrier Sense disabled	0	RW
	Sense Disable	0	= Transmit Carrier Sense enabled
		0	= Transmit Carrier Sense enabled

8	Disable Dynamic	1	= Dynamic Power-Down disabled	0	RW
	Power-Down	0	= Dynamic Power-Down enabled (normal)
		0	= Dynamic Power-Down enabled (normal)

7	Auto-Negotiation	1	= Auto-Negotiation loopback	0	RW
	Loopback	0	= Auto-Negotiation normal mode
		0	= Auto-Negotiation normal mode

6	MDI Tri-State	1	= MDI Tri-state (transmit driver tri-states)	0	RW
		0	= Normal operation

5	Filter By-pass	1	= By-pass filter	0	RW
		0	= Normal filter operation

4	Auto Polarity	1	= Auto Polarity disabled	0	RW
	Disable	0	= Normal polarity operation
		0	= Normal polarity operation

3	Squelch Disable	1	= 10BASE-T squelch test disable	0	RW
		0	= Normal squelch operation

2	Extended	1	= 10BASE-T Extended Squelch control enabled	--	RW
	Squelch	0	= 10BASE-T Extended Squelch control disabled
		0	= 10BASE-T Extended Squelch control disabled

1	Link Integrity	1	= Link disabled	0	RW
	Disable	0	= Normal Link Integrity operation
		0	= Normal Link Integrity operation

0	Jabber Function	1	= Jabber disabled	0	RW
	Disable	0	= Normal Jabber operation
		0	= Normal Jabber operation

7.2.3.3Register 20: 100BASE-TX Receive Disconnect Counter Bit Definitions

Bit(s)	Name	Description	Default	R/W


15:0	Disconnect Event	This field contains a 16-bit counter that increments for	--	RO
		each disconnect event. The counter stops when full		SC
		(and does not roll over) and self-clears on read		SC
		(and does not roll over) and self-clears on read
		In repeater mode, a frame that starts without “JK” is a
		disconnect event.

7.2.3.4Register 21: 100BASE-TX Receive Error Frame Counter Bit Definitions

Bit(s)	Name	Description	Default	R/W


15:0	Receive Error	This field contains a 16-bit counter that increments	--	RO
	Frame	once per frame for any receive error condition (such		SC
		as a symbol error or premature end of frame) in that		SC
		as a symbol error or premature end of frame) in that
		frame. The counter stops when full (and does not roll
		over) and self-clears on read.

Datasheet

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Contents 82555 10/100 Mbps LAN Physical Layer Interface Product FeaturesRevision Description Networking SiliconContents Repeater Mode Functional Overview IntroductionCompliance to Industry Standards Networking Silicon Architectural Overview 100 Mbps ModeMII TX Interface 10 Mbps ModeMedia Independent Interface MII Repeater mode only Transmit Error From RICYes Pin Numbers and Labels Pin DefinitionsTwisted Pair Ethernet TPE Pins Clock PinsMedia Independent Interface MII Pins Pin TypesMedia Access Control/Repeater Interface Control Pins External Bias Pins LED PinsMiscellaneous Control Pins VCC Power and Ground PinsVSS Symbol 5B Symbol Code 4B Nibble Code 100BASE-TX Adapter Mode Operation100BASE-TX Transmit Clock Generation 100BASE-TX Transmit BlocksInvalid 2 100BASE-TX Scrambler and MLT-3 Encoder3 100BASE-TX Transmit Framing NRZ to MLT-3 Encoding DiagramTransmit Driver 100BASE-TX Receive BlocksVendor Model/Type 100BASE-TX Collision Detection Combination Tx/T4 Auto-Negotiation Solution 100BASE-TX Link Integrity and Auto-Negotiation SolutionLink Integrity Auto-NegotiationAuto 10/100 Mbps Speed Selection Adapter Mode AddressesNetworking Silicon Datasheet 10BASE-T Transmit Clock Generation 10BASE-T Functionality in Adapter Mode10BASE-T Transmit Blocks 10BASE-T Receive Blocks10BASE-T Collision Detection 3 10BASE-T Error Detection and Reporting10BASE-T Link Integrity 10BASE-T Jabber Control Function10BASE-T Full Duplex Networking Silicon Datasheet Special Repeater Features Repeater ModeConnectivity Clock Signal Example MDI Frame Structure Management Data InterfaceMDI Registers Bits Name Description DefaultMDI Registers 0 Transition10BASE-T Register 1 Status Register Bit DefinitionsRegister 2 82555 Identifier Register Bit Definitions MDI Registers 16 MDI Registers 8100BASE-TX Register 17 82555 Special Control Bit Definitions150 Actled Liled Register 22 Receive Symbol Error Counter Bit DefinitionsAuto-Negotiation Functionality Bit Setting TechnologyDescription Priority TechnologyPriority Parallel Detect and Auto-NegotiationAuto-Negotiation and Parallel Detect Networking Silicon Datasheet LED Descriptions Networking Silicon Datasheet Reset Reset and Miscellaneous Test ModesLoopback Scrambler BypassNumber Code Test Instruction Select Input to Tout Test Instruction CodingDC Characteristics Electrical Specifications and Timing ParametersAbsolute Maximum Ratings General Operating ConditionsTotal supply current 230 Leakage on analog pins 11.3.3 100BASE-TX Voltage/Current DC CharacteristicsMII Clock Specifications AC CharacteristicsSymbol Parameter Conditions Min Typ Max Units MII Clocks AC Timing MII Timing ParametersRXC tri-stated a Repeater Mode Timing ParametersSquelch Test Timing Parameters Transmit Packet Timing ParametersReceive Packet Timing Parameters Jabber Timing ParametersAuto-Negotiation Fast Link Pulse FLP Timing Parameters 11.4.8 10BASE-T Normal Link Pulse NLP Timing Parameters11.4.11 X1 Clock Specifications Reset Timing ParametersX1 Clock Specifications 11.4.12 100BASE-TX Transmitter AC Specification12.0 82555 Package Information Symbol Description Min Norm Max10.0